• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• ETRI Journal
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• v.24 no.2
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• pp.161-171
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• 2002

This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

• Proceedings of the SAREK Conference
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• 2005.11a
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• pp.433-438
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• 2005

An AHX(Accumulator Heat eXchanger) consists of a commercial accumulator and an inner heat exchanger located inside of the accumulator. The AHX is used in multi air-conditioners to assure the liquid-phase refrigerant entering into the expansion device. This purpose is achieved by heat transfer between the refrigerant leaving the evaporator and the refrigerant leaving the condenser. In this study, the effects of AHX on the performance of a refrigeration system using H-22 were measured and the test results were analyzed. The operating characteristics of the refrigeration system with the installation of AHX were quite different from those without the installation of AHX. Therefore, it is required to find an optimum refrigerant charging amount and optimum operating conditions, when AHX is installed in the refrigeration system with an fixed area expansion device such as a capillary tube.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.18 no.5
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• pp.418-425
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• 2006

An AHX (Accumulator Heat exchanger) consists of a commercial accumulator and an inner heat exchanger located inside of the accumulator. The AHX is used in multi air-conditioners to assure that liquid-phase refrigerant enters into the expansion device. This purpose is achieved by heat transfer between the refrigerant leaving the evaporator and the refrigerant leaving the condenser. In this study, the effects of AHX on the performance of a refrigeration system using R-22 were measured and the test results were analyzed. The operating characteristics of the refrigeration system with the AHX are considerably different from those without the AHX. Therefore, it is required to determine optimum refrigerant charge and optimum operating conditions when the AHX is used in the refrigeration system having a constant flow-area expansion device such as capillary tube.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.126-137
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. And we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.2046-2054
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• 1989

Improved algorithms are presented to design linear phase digital FIR filters with coefficients of +1,0,-1 only followed by a multiple integrator. It has been shown that the existing linear phase filter design concept for the single integrator(or, accumulator)case can be extended to the case of the multiple integrator. Linear phase conditions for the multiple integrators are summarized. Filter design methods with double or triple integrator are exploited in datail and its computer simulation results are presented to deduce the advantages of multiple integrator to the single integrator.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.291-297
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• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.275-275
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• 2000

This paper designs a digital correlator for the integrated GPS/GLONASS receiver consisting of DCO, carrier cycle counter, code generator, code phase counter, mixer, epoch counter, accumulator. It is designed using Verilog-HDL(Verilog-Hardware Description Language) and synthesized using EDA(Electronic Design Automation) tools. The performance of the designed digital correlator is verified by the functional simulation and real satellite tracking experiments.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2033-2038
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• 2008

The CPLs(capillary pumped loops) are two phase heat transfer devices which enable active control of operating temperature of heat absorbing elements(or evaporators). Although the CPLs gain increasing interests as promising heat transfer devices for future missions such as spacecraft and commercial applications, their intrinsic complexity in operating principles makes the widespread use of these devices difficult. The key element and main cause of this complexity in operating principles is the two phase hydrodynamic accumulator or reservoir which controls the saturation state of the remaining loop and, particularly for the CPLs, it is separated from the evaporator. Thus, in this study, the operating characteristics of the CPL is investigated experimentally and theoretically. Mainly focusing on the role of reservoir the thermodynamic operating principle is examined first and the experimentally obtained steady state and transient state operating characteristics are discussed in detail.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.9
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• pp.103-110
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• 2004

Pressure ripples yield noise and vibration in hydraulic pipelines, which are inevitably generated by a fluctuation of flow rate in the pump mechanism, and such noise and vibration deteriorate the stability and accuracy of hydraulic systems. To reduce the pressure ripples, accumulator and hydraulic attenuator are normally used. In this study, parallel pipeline with a bent-axis piston pump is introduced to a hydraulic pipe system as a method for reducing the pressure ripples and using the transfer matrix method, the dynamic characteristics of the pipe system are analysed and compared with experimental results. The results show that the phase interference using parallel pipeline with a bent-axis piston pump is effective to reduce the pressure ripples in the hydraulic pipelines.