• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.11
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• pp.106-115
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• 1996

In this paper, the method using virtual scheduling suggested algorithm (VSSA) is suggested by considering cell delay variation and token rate of leaky bucket. This method is compared with virtual scheduling algorithm (VSA) and virtual scheduling algorithm with no tolerance excessive peak cell rate. As a result, the research shows that the usage parameter control using vSSA makes quality of service better than the usage parameter control using vSA or VSANT does because the suggested method reduces the violated cell probability of conformed peak cell rate and intentionally excessive peak cell rate.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1376-1377
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• 2008

가스절연변압기(GITr)는 우수한 절연내력과 높은 신뢰성을 장점으로 가지고 있지만, 제작과 운전 단계에서 절연 결함이 발생할 수 있고 이러한 결함들은 가스절연변압기 사고의 원인이 될 수 있다. 따라서 결함에 대한 상시 진단 및 원인 분석이 반드시 선행되어야 하며 이와 같은 진단 분석 기법의 하나로 내부 절연결함의 위치 판별에 대한 연구의 필요성이 절실히 요구되고 있다. 따라서 본 논문에서는 일반적으로 부분 방전의 위치 판별을 위한 time delay 측정법 중 하나인 Cross-correlation 방법과 함께 제안한 Threshold-Initial peak detection 방법을 적용하여 위치 데이터를 취득하고 신뢰구간 이내의 데이터만 사용하여 부분 방전 위치 판별 한 결과, 더욱 정확한 위치 판별이 가능하였다.

• Journal of Korean Port Research
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• v.8 no.2
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• pp.1-35
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• 1994

The main arterial which runs through the in City of Pusan, carries about 60% of downtown traffic or more, maintains about 20% yearly increase in traffic is severely suffering from the traffic congestion because of concentrated traffic volumes regardless of peak-time periods. The purpose of this study was to grasp the traffic, geometric, and signal conditions of the main arterial through the Videologging System Techniques, perform the transportation system analyses, and finally suggest the improvements which could increase the travel capacity, reduce the average delay and fuel consumption with the optimal conditions of signal system. The following conclusions were drawn : firstly the traffic system should be shifted for the travel distribution on the arterial during the peak time periods, secondly the roadway system of the arterial reviewed for left-turn traffic during the peak time periods, and thirdly the signal system of intersection reconstructed for signal optimization or progression within the range of cycle length suggested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• ETRI Journal
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• v.34 no.1
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.8
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• pp.52-57
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• 2012

We propose a weighted time-reversal prefilter for indoor wireless communication systems. In the indoor wireless communication environments, the bit error rate (BER) performance is significantly degraded by the delay spread. The conventional schemes have complex receivers to recover deterioration of the BER. The proposed time-reversal prefilter simplifies the structure of receivers, minimizes the inter-symbol interference (ISI) and maintains the peak power level of the received signal. The simulation results show that the weighted time-reversal prefilter improves the BER performance in comparison with the conventional time-reversal prefilter.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• IEIE Transactions on Smart Processing and Computing
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• v.1 no.3
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• pp.152-160
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• 2012

This paper proposes a frame-level rate control algorithm for low delay video applications to reduce the fluctuations in the bitrate. The proposed algorithm minimizes the bitrate fluctuations in two ways with minimal coding loss. First, the proposed rate control applies R-Q model to all frames including the first frame of every group of pictures (GOP) except for the first one of a sequence. Conventional rate control algorithms do not use any R-Q models for the first frame of each GOP and do not estimate the generated-bit. An unexpected output rate result from the first frame affects the remainder of the pictures in the rate control. Second, a rate-distortion (R-D) cost is calculated regardless of the hierarchical coding structure for low bitrate fluctuations because the hierarchical coding structure controls the output bitrate in rate distortion optimization (RDO) process. The experimental results show that the average variance of per-frame bits with the proposed algorithm can reduce by approximately 33.8% with a delta peak signal-to-noise ratio (PSNR) degradation of 1.4dB for a "low-delay B" coding structure and by approximately 35.7% with a delta-PSNR degradation of 1.3dB for a "low-delay P" coding structure, compared to HM 8.0 rate control.