• Current Photovoltaic Research
• /
• v.1 no.1
• /
• pp.69-72
• /
• 2013

Combined nano- and micro-wires (CNMWs) Si arrays were prepared using PR patterning and silver-assisted electroless etching. A $POCl_3$ doping process was applied to the fabrication of CNMWs solar cells. KOH solution was used to remove bundles in CNMWs and the etching time was varied from 30 to 240 s. The lowest reflectance of 3.83% was obtained at KOH etching time of 30 s, but the highest carrier lifetime of $354{\mu}s$ was observed after the doping process at 60 s. At the same etching time, a $V_{oc}$ of 574 mV, $J_{sc}$ of $28.41mA/cm^2$, FF of 74.4%, and Eff. of 12.2% were achieved in the CNMWs solar cell. CNMWs solar cells have potential for higher efficiency by improving the post-process and surface-rear side structure.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.105-106
• /
• 2006

The ferroelectric materials of the PZT, SBT attracted much attention for application to ferroelectric random access memory (FRAM) devices. Through the last decade, the lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for the ferroelectric products due to its higher remanant polarization and the ability to withstand higher coercive fields. FRAM has been currently receiving increasing attention for one of future memory devices due to its ideal memory properties such as non-volatility, high charge storage, and faster switching operations. In this study, we first applied the damascene process using chemical mechanical polishing (CMP) to the fabricate the $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ thin film capacitor in order to solve the problems of plasma etching such as low etching profile and ion charging. The structural characteristics were compared with specimens before and after CMP process of PZT films. The scanning electron microscopy (SEM) analysis was performed to compare the morphology surface characteristics of $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ capacitors. The densification by the vertical sidewall patterning and charging-free ferroelectric capacitor could be obtained by the damascene process without remarkable difference of the characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.545-545
• /
• 2007

Recently, innovative process has been investigated in order to replace the conventional high-cost micro patterning processes on the electronic products. To produce desirable profit margins from this low cost products, printed circuit board(PCB), will require dramatic changes in the current manufacturing philosophies and processes. Innovative process using metal nano particles replaces the current industry standard of subtractive etched of copper as a highly efficient way to produce robust circuitry on low cost substrates. An advantage of using metal nano particles process in patterned conductive line manufacturing is that the process is additive. Material is only deposited in desired locations, thereby reducing the amount of chemical and material waste. Simply, it just draws on the substrate as glass epoxy or polyimide with metal nano particles. Particles, when their size becomes nano-meter scale, show some specific characteristics such as enhanced reactivity of surface atoms, decrease in melting point, high electric conductivity compared with the bulk. Melting temperature of metal gets low, the metal nano particles could be formated onto polymer substrates and sintered under $300^{\circ}C$, which would be applied in PCB. It can be getting the metal line of excellent electric conductivity.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.433-433
• /
• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.196-203
• /
• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.2
• /
• pp.1-6
• /
• 2000

X-ray lithography mask with SiC membrane and Ta absorber patterns has been fabricated using ECR plasma CVD, d.c. magnetron sputtering, and ECR plasma etching. The stress of stoichiometric SiC film was adjusted by rapid thermal annealing under $N_2$, ambient. Adjusting the working pressure during sputtering process resulted in a near-zero residual stress, reasonable density, and smooth surface morphology of Ta film. Cl-based plasma showed a good etching characteristics of Ta, and two-step etching process was implemented to suppress microloading effect fur sub-quarter $\mu\textrm{m}$ patterning.

• Laser Solutions
• /
• v.16 no.4
• /
• pp.12-16
• /
• 2013

For mass production of electronic devices, the processing of the printing roll is one of the most important key technologies for printed electronics technology. A roll of printing process, the gravure printing that is used to print the electronic device is most often used. The indirect laser processing has been used in order to produce printing roll for gravure printing. It consists of the following processing that is coating of photo polymer or black lacquer on the surface of printing roll, pattering using a laser beam and etching process. In this study, we have carried out study on the coating and etching for $25{\mu}m$ line width on the printing roll. To do this goals, a $4{\mu}m$ coating thickness and 20% average coating thickness of the coating homogeneity of variance is performed. The factors to determine the thickness and homogeneity are a viscosity of coating solution, the liquid injection, the number of injection, feed rate, rotational speed, and the like. After the laser patterning, a line width of $25{\mu}m$ or less was confirmed to be processed through etching and the chromium plating process.

• Journal of the Korean Society for Precision Engineering
• /
• v.22 no.12 s.177
• /
• pp.184-189
• /
• 2005

An experimental study of the femtosecond laser machining of Si materials was carried out. Direct laser machining of the materials for the feature size of a few micron scale has the advantage of low cost and simple process comparing to the semiconductor process, E-beam lithography, ECM and other machining process. Further, the femtosecond laser is the better tool to machine the micro parts due to its characteristics of minimizing the heat affected zone(HAZ). As a result of line cutting of Si, the optimal condition had the region of the effective energy of 2mJ/mm-2.5mJ/mm with the power of 0.5mW-1.5mW. The polarization effects of the incident beam existed in the machining qualities, therefore the sample motion should be perpendicular to the projection of the electric vector. We also observed the periodic ripple patterns which come out in condition of the pulse overlap with the threshold energy. Finally, we could machined the groove with the linewidth of below $2{\mu}m$ for the application of MEMS device repairing, scribing and arbitrary patterning.

• Transactions on Electrical and Electronic Materials
• /
• v.9 no.4
• /
• pp.163-168
• /
• 2008

Photonic crystal structures have been received considerable attention due to their high optical sensitivity. One of the techniques to construct their structure is the dip-pen lithography (DPN) process, which requires a nano-scale resolution and high reliability. In this paper, we propose a two dimensional photonic crystal array to improve the sensitivity of optical biosensor and DPN process to realize it. As a result of DPN patterning test, we have observed that the diffusion coefficient of the mercaptohexadecanoic acid (MHA) molecule ink in octanol is much larger than that in acetonitrile. In addition, we have designed and fabricated optical waveguides based on the mach-zehnder interferometer (MZI) for application to biosensors. The waveguides were optimized at a wavelength of 1550 nm and fabricated according to the design rule of 0.45 delta%, which is the difference of refractive index between the core and clad. The MZI optical waveguides were measured of the optical characteristics for the application of biosensor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.6
• /
• pp.462-467
• /
• 2013

In this paper, we analyzed the effects of doctoring process on the patterns of Ag ink in gravure off-set printing. The parameters of doctoring process were the angle and the pressure, which was represented by the depth of blade movement to the gravure roll, of doctor blade to the surface of gravure roll, and the angle of patterns engraved on the gravure roll to the doctor blade moving direction. The proper parameters were extracted for the fine patterns and they were 15 mm for the pressure, $60^{\circ}$ for the blade angle. And the angle of patterns with respect to the blade movement should be less than $40^{\circ}$ for the best results. The gravure off-set printing with the above parameters was carried out to print gate electrodes and scan bus lines of OTFT-backplane for e-paper. The line width of $50{\mu}m$ was successfully obtained. The thickness of electrodes was $2.5{\mu}m$ and the surface roughness was $0.65{\mu}m$ and the sheet resistance was $15.8{\Omega}/{\Box}$.