• 한국통신학회논문지
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• 제37A권11호
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• pp.972-978
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• 2012

LDPC(low density parity check)부호는 합-곱 알고리즘 기반의 반복복호를 통해 Shannon 한계에 근접하는 성능을 보인다. 합곱 알고리즘에서 체크노드와 비트노드의 확률 및 부가정보의 갱신 순서는 스케쥴링 방법에 따라 달라지며 그에 따라 오류정정능력이나 반복복호의 횟수가 달라진다. 기존에 제안된 순차 BP 알고리즘을 사용한 LDPC의 복호는 표준 BP 알고리즘을 바탕으로 복호를 수행했을 경우에 비해 적은 평균반복복호 횟수에도 불구하고 좋은 성능을 가진다고 알려져 있다. 하지만 기존의 연구들에서는 이러한 성능 차이의 원인에 대한 연구는 미비하다. 따라서 본 논문에서는 두 알고리즘의 적용에 따른 LDPC 복호의 성공 여부에 따라 4가지 경우로 분류하고 각 경우를 비교한다. 이를 통해 두 알고리즘의 성능 차이의 원인을 분석하고 그 결과로 성능 차이의 원인이 패리티 검사행렬 내부의 사이클을 구성하는 비트노드들의 확률 값을 갱신할 때 알고리즘에 따른 갱신 과정의 차이에 있음을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• 한국통신학회논문지
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• 제29권10C호
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• pp.1363-1369
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• 2004

LDPC 부호의 검사행렬은 비트노드와 검사노드간의 이분 그래프로 표현된다. Tanner는 그래프상의 인접 행렬 (adjacency matrix) 고유값을 이용하여, 균일 LDPC 부호의 최소 거리 하한식(minimum 야stance bound)을 유도하였다. 본 논문에서는 Tanner의 결과를 일반화하여, 균일 및 블록 구조를 갖는 비균일 LDPC부호에 적용 가능한 두개의 최소 거리 하한식을 유도한다. 첫 번째는 최소 거리 부호어에 인접한 비트노드들의 관계를 통하여 유도되는 비트노드 기반 하한식이고, 두 번째는 최소 거리 부호어와 연접한 검사노드들의 관계에서 얻어지는 검사노드기반 하한식이다. 론 논문에서 유도한 하한식을 통하여 블록 구조를 갖는 비균일 LDPC부호의 거리 특성을 그래프의 고유값들과의 관계로 나타낼 수 있다.

• Journal of Communications and Networks
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• 제17권4호
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• pp.346-350
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• 2015

It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

• Journal of Communications and Networks
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• 제10권1호
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• pp.5-9
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• 2008

Researchers have investigated many upper bound techniques applicable to error probabilities on the maximum likelihood (ML) decoding performance of turbo-like codes and low density parity check (LDPC) codes in recent years for a long codeword block size. This is because it is trivial for a short codeword block size. Previous research efforts, such as the simple bound technique [20] recently proposed, developed upper bounds for LDPC codes and turbo-like codes using ensemble codes or the uniformly interleaved assumption. This assumption bounds the performance averaged over all ensemble codes or all interleavers. Another previous research effort [21] obtained the upper bound of turbo-like code with a particular interleaver using a truncated union bound which requires information of the minimum Hamming distance and the number of codewords with the minimum Hamming distance. However, it gives the reliable bound only in the region of the error floor where the minimum Hamming distance is dominant, i.e., in the region of high signal-to-noise ratios. Therefore, currently an upper bound on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix cannot be calculated because of heavy complexity so that only average bounds for ensemble codes can be obtained using a uniform interleaver assumption. In this paper, we propose a new bound technique on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix using ML estimated weight distributions and we also show that the practical iterative decoding performance is approximately suboptimal in ML sense because the simulation performance of iterative decoding is worse than the proposed upper bound and no wonder, even worse than ML decoding performance. In order to show this point, we compare the simulation results with the proposed upper bound and previous bounds. The proposed bound technique is based on the simple bound with an approximate weight distribution including several exact smallest distance terms, not with the ensemble distribution or the uniform interleaver assumption. This technique also shows a tighter upper bound than any other previous bound techniques for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제6권1호
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• pp.47-52
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• 2002

In this paper we propose a simple decoding algorithm for the 4-ary lexicographic codes (or lexicodes) of length 10 with minimum distance 4, write $S_{10,4}$. It is based on the syndrome decoding method. That is, using a syndrome vector we detect an error and it will be corrected an error from the four parity check equations.

• 한국전자통신학회논문지
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• 제7권1호
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• pp.117-124
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• 2012

본 논문에서는 cycle-4를 쉽게 피하고 가변 부호율과 길이로 접근할 수 있게 하는 순환 치환 행렬(CPM; circulant permutation matrix)을 토대로 한 간단한 패리티 검사 행렬의 구성 방법을 제안한다. 결과적으로 부행렬 연산은 여러 CPM들의 곱셈으로 처리될 수 있으며 LDPC 부호화 계산은 매우 간단하게 수행된다. 또한 LDPC 부호의 고속 부호화 문제를 고려한다. 제안한 설계는 정규, 비정규 LDPC 부호 둘 다를 위한 간단한 행렬 연산에 근거한 고속 부호화를 가능하게 한다.

• 한국통신학회논문지
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• 제39C권8호
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• pp.637-642
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• 2014

본 논문은 블록 LDPC(low density parity check) 부호 설계를 위한 순환 천이 값(shift index)을 탐색하는 효율적인 알고리즘을 제안한다. 여기에는 메시지-패싱(message-passing) 기반의 순환 주기(cycle) 탐색 알고리즘과 ACE(approximate cycle extrinsic message degree) 알고리즘이 결합되어 있다. LDPC 부호 성능에 영향을 미치는 요인들에 우선순위를 두어 효율적으로 순환 천이 값을 찾을 수 있도록 했다. 이 알고리즘을 통해 기존의 탐색 알고리즘 보다 훨씬 낮은 복잡도로 행렬 저장 공간을 절약하면서 좋은 성능의 패리티 검사 행렬(parity check matrix)을 만들 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.323-326
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• 2002

In this paper, we study the improved bounds on the performance of low-density parity-check (LDPC) codes over binary-input additive white Gaussian noise (AWGN) channels with belief propagation (BP) decoding in log domain. We define an extended Gallager ensemble based on a new method of constructing parity check matrix and make use of this way to improve upper bound of LDPC codes. At the same time, many simulation results are presented in this paper. These results indicate the extended Gallager ensembles based on Hamming codes have typical minimum distance ratio, which is very close to the asymptotic Gilbert Varshamov bound and the superior performance which is better than the original Gallager ensembles.