• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.724-729
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• 2007

In this paper, we propose a new diagnosis method of DC/DC converter aging. The method is based on variations of the parasitic resistor for the aging process. We apply an on-line diagnosis of the DC/DC converter because the observation is not a device, but a system. This study proposes a method of DC/DC converter diagnosis by analyzing the variations of model on the variations of parasitic resistor.

• Proceedings of the KIEE Conference
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• summer
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• pp.1275-1277
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• 2004

In this paper, we propose a new diagnosis method of DC/DC converter aging. The method is based on the variations of parasitic resistor for the aging process. We apply an on-line diagnosis of DC/DC converter because the observation is not a device, but a system. This study proposes a method of DC/DC converter diagnosis by analyzing the variations of model on the variations of parasitic resistor.

• Proceedings of the KIEE Conference
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• summer
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• pp.1278-1280
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• 2004

In this paper, we propose a new diagnosis method of DC/DC converter aging. The method is based on the variations of parasitic resistor for the aging process. We apply an on-line diagnosis of DC/DC converter because the observation is not a device, but a system. This study proposes a method of DC/DC converter diagnosis by analyzing the variations of model on the variations of parasitic resistor.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.20-32
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• 1997

An optimum parasitic inductance is observed for maximizing the modulation bandwidth of the multiple quantum well (MQW) electro-absorption optical modulator. For 1.1 pF device cpaacitance of the current MQW optical modulator, the optimum parasitic inductances for maximum bandwidth are calculated for different terminating resistors. In ase of 50.ohm. terminating resistor, the 3-dB modulation bandwidth can be increased 45% wider by using the optimum parasitic inductance than nothing parasitic inductance. This calculated optimum inductance can be practically implemented, since the parasitic inductance of bondwires can be accurately analyzed using the method of moments (MoM) and controlled by changing the length and shpae of bondwires.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.11-18
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• 1997

By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.5
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• pp.10-19
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• 1971

Problems and technologies involved in integrating an audio preamplifier in terms of thick film technology has been discussed in detail. In particular, an attempt has been made to find methods for functional trimming of the amplifer by employing computer analysis. Among seven resistors integrated on a alumina substrate, only one resistor was found to be very sensitive to over all performance of the preamplifier. By trimming this resistor to its freguency charcteristic reguirements, it was possible to cut down trimming labor by one seventh. Besides, problems concerning resistor conductor contacts, crossover parasitic capacitance and the relations between noise per(ormance and trimming method are discussed in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.484-492
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• 2015

This paper proposes a PWM phase-shift circuit to make that the LED lighting system distributes the channel currents evenly for any number of LED strings by generating evenly phase-shifted PWM signals for multiple LED driver ICs. The evenly distributed channel currents reduce the peak current, the decoupling capacitor size, and EMI noise. The PWM phase-shift circuit makes an arbitrary degree of PWM phase-shift by using a resistor and a capacitor. It measures the RC delay once. It reduces the number of external resistors and capacitors by providing zero and 180 degree phase-shift modes requiring no resistor and capacitor. An LED driver IC with the PWM phase-shift circuit was fabricated with a $0.35{\mu}m$ BCDMOS process. The PWM phase-shift circuit receives a PWM signal of 50 Hz~20 kHz at $f_{CLK}=450kHz$ and it generates a $0{\sim}360^{\circ}$ phase-shifted PWM signal with $R=0{\sim}1.1M{\Omega}$ at C=1 nF and $f_{PWM}=1kHz$. The measured phase errors are 1.74~3.94% due to parasitic capacitances.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.559-560
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• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.635-639
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• 2016

In the devices used in the microwave frequency band, the gain decreases as the frequency increases due to the parasitic component. To compensate for these characteristics, a linear gain equalizer with an opposite slope is needed in wideband systems, such as those used for electronic warfare. In this study, a linear gain equalizer that can be used in the 18 ~ 40GHz band is designed and fabricated. Circuit design and momentum design (optimizations) were carried out to reduce the errors between design and manufacturing. A thin film process is used to minimize the parasitic components within the implementation frequency band. A sheet resistance of 100 ohm/square was employed to minimize the wavelength variation due to the length of the thin film resistor. This linear gain equalizer is a structure that combines a quarter wavelength-resonator on a series microstrip line with a resistor. All three 1/4 wavelength short resonators were used. The fabricated linear gain equalizer has a loss of more than -5dB at 40GHz and a 6dB slope in the 18 ~ 40GHz band. By using the manufactured gain equalizer in a multi-stage connected device such as an electronic warfare receiver, the gain flatness degradation with increasing frequency can be reduced.