• 전기학회논문지
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• 제67권4호
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• 전기학회논문지
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• 제56권4호
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• pp.683-692
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• 2007

An inverter driven induction motor has more superior dynamic characteristic than sine wave driven induction motor. But it has a problem with shaft voltage and bearing current in drive-motor system. This paper presents the analysis of bearing current in inverter-fed induction motor. The proposed method is based on using numerical method (FEM) to derive parasitic parameters in motor. Using the electric field analysis with FEM, the stored energy in dielectric materials of the motor can be calculated and the parasitic capacitances are obtained. Then we compared the proposed method with a conventional method in variable frequency and load conditions. From the comparision of simulation and experiment result, we confirmed that the proposed method is valid.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권12호
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• pp.773-776
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• 1999

A newly proposed lateral dual-gate thyristor was fabricated and measured, which has excellent current saturation characteristics of $1200A/cm^2$ even at an anode-gate voltage of 29V, through the elimination of the structurally existing parasitic thyristor. And through the comparison with the LIGBT, the excellent current saturation characteristics of a newly proposed device was verified.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.1-5
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• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• 대한전자공학회논문지
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Parasites, Hosts and Diseases
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• 제59권6호
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• pp.615-623
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• 2021

Human sparganosis is a food-borne parasitic disease caused by the plerocercoids of Spirometra species. Clinical diagnosis of sparganosis is crucial for effective treatment, thus it is important to identify sensitive and specific antigens of plerocercoids. The aim of the current study was to identify and characterize the immunogenic proteins of Spirometra erinaceieuropaei plerocercoids that were recognized by patient sera. Crude soluble extract of the plerocercoids were separated using 2-dimensional gel electrophoresis coupled with immunoblot and mass spectrometry analysis. Based on immunoblotting patterns and mass spectrometry results, 8 antigenic proteins were identified from the plerocercoid. Among the proteins, cysteine protease protein might be developed as an antigen for diagnosis of sparganosis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.392-395
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• 2003

For the first time, the new dual trench gate Emitter Switched Thyristor is proposed for eliminating snap-back effect which leads to a lot of serious problems of device applications. Also, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in the proposed EST structure, allowing higher maximum controllable current densities for ESTs. Moreover, the new dual trench gate allows homogenous current distribution throughout device and preserves the unique feature of the gate controlled current saturation of the thyristor current. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $354/{\S}^2$, respectively. But the proposed EST exhibits snap-back with the anode voltage and current density 0.93V and $58A/{\S}^2$, respectively. Saturation current density of the proposed EST at anode voltage 6.11V is $3797A/{\S}^2$. The characteristics of 700V forward blocking of the proposed EST obtained from two dimensional numerical simulations (MEDICI) is described and compared with that of the conventional EST.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.105-106
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• 2016

In low-power grid-connected photovoltaic(PV) system, Single-phase transformerless full-bridge inverter is commonly used. However in transformerless photovoltaic application, the ground parasitic capacitance created by grounding between PV panels and ground. This ground parasitic capacitance inject additional current into the inverter, these currents cause electromagnetic interference problem, safety problem and harmonics problem in PV applications. In order to eliminate the ground current, This paper propose various inverter topologies in PV applications. These proposed inverter topologies are verified through simulation using PSIM.

• 전기전자학회논문지
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• 제8권1호
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• pp.63-72
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• 2004

The supply voltage has been drop rapidly and the total length of the wire increased exponentially in the nanometer SoC design environment. The ideal supply voltage was dropped sharply by the resistance and parasitic devices which stayed on the kilometers-long wire length. Even worse, it could severely affect the functional behavior of the block of the design. To analyze the effects of the long wire of the SoC while maintaining the accuracy, the modeling of the current and the RC conversion of the parasitic techniques are researched and applied. By these modeling and conversion, the multi-million gates HDTV Chipset can be analyzed within a day. The benchmark analysis of the HDTV SoC showed the superiority to the conventional methods in performance and accuracy.