• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.1
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• pp.94-102
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• 2015

The electronic ballast for HID lamps needs to ignite lamps even though the length from the ballast to lamp is far away. Therefore, it needs to do the research on a resonant ignition to turn on the HID lamps because the reduction of ignition voltage is not much depending on the distance. However, the parasitic capacitance is increased depending the length of the cable, and it affects the resonant frequency. The ignitor voltage can be increased drastically under the resonant ignition through frequency sweep, and it is the main reason of blowing up. Therefore, the clamping diode is proposed to suppress the voltage of the primary winding during resonant ignition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.85-91
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• 2008

A Boost Power Factor Correction (PFC) Converter employing Zero Voltage Switching (ZVS) based Compound Active Clamping (CAC) technique is presented in this paper. An Electro Magnetic Interference (EMI) Filer is connected at the line side of the proposed converter to suppress Electro Magnetic Interference. The proposed converter can effectively reduce the losses caused by diode reverse recovery. Both the main switch and the auxiliary switch can achieve soft switching i.e. ZVS under certain condition. The parasitic oscillation caused by the parasitic capacitance of the boost diode is eliminated. The voltage on the main switch, the auxiliary switch and the boost diode are clamped. The principle of operation, design and simulation results are presented here. A prototype of the proposed converter is built and tested for low input voltage i.e. 15V AC supply and the experimental results are obtained. The power factor at the line side of the converter and the converter efficiency are improved using the proposed technique.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2151-2155
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• 1998

The traveling wave type ultrasonic motor(USM) has no electro-magnetic circuits( coil or core). The driving principle of the USM is based on high-frequency mechanical vibrations and frictional force. The USM, thus, is fed by two-phase high - frequency sinusoidal inverter using its series resonant parasitic components. For the using of series resonant type inverter, it should be needed to a USM parasitic capacitance and a proper inductor chosen. In this paper, the values of optimal inductance are designed and the efficiency of USM drives is achieved. The effectiveness of the proposed design is demonstrated by experiments.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.4
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• pp.672-678
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• 1994

A design of 5th-order Elliptic OTA-C filter for operation at 4.2MHz is presented. the filter structure is composed entirely of five OTAs(Operational transoonductance Amplifiers), one buffer and seven capacitors. To prevent decreasing of frequency charaoteristios due to the parasitic effeots of OTA and buffer, the design considering of parasitic capacitance and finite resistane of OTA and fuffer is pertormed. As the result of the simulation using SPICE with $2{\mu}m$ CMOS parameters, The performances were found to be essentially within the specifications` less than 0.25dB passband attenuation, 30dB stopband attenuation and 4.2MHz cut-off frequency were satisfactorily obtained. The number of elements is also considerably reduced than other design methods.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.612-614
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• 1998

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

• Journal of Power Electronics
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• v.5 no.4
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.56-61
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• 2019

In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a $1{\mu}F$ parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.1
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• pp.70-77
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• 2005

A new converter to transfer energy from a low-voltage AC current source to a battery is proposed. It is focused to find operational modes of the converter. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge MOSFET rectifier and a MOSFET boost converter in order to make the converter small and efficient. The operational principle and modes of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs and diode. The results are proved with simulation studies using PSIM and Pspice.