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http://dx.doi.org/10.6113/TKPE.2019.24.1.56

Development of Leakage Current Reduction Method in 3-Level Photovoltaic PCS  

Han, Seongeun (Dept. of Electrical Engineering, Chungnam National University)
Jo, Jongmin (Dept. of Electrical Engineering, Chungnam National University)
An, Hyunsung (Dept. of Electrical Engineering, Chungnam National University)
Cha, Hanju (Dept. of Electrical Engineering, Chungnam National University)
Publication Information
The Transactions of the Korean Institute of Power Electronics / v.24, no.1, 2019 , pp. 56-61 More about this Journal
Abstract
In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a $1{\mu}F$ parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method.
Keywords
Leakage current; Photovoltaic PCS; 3-level inverter; Common mode voltage;
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