• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.5
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• pp.640-651
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• 2000

For the heat and fluid flow analyses of a parallel flow heat exchanger, an improved model considering the effect of flat tube with micro-channels is proposed. The effect of flow distribution on the thermal performance of a heat exchanger is numerically investigated. The flow distribution is examined by varying geometrical parameters, i.e., the position of the separators and the inlet/outlet, and the aspect ratio of micro-channels of the heat exchanger. The flow nonuniformities along the paths of the heat exchanger are proposed and observed to evaluate the thermal performance of the heat exchanger. The optimization using ALM method has been accomplished by minimizing the flow nonuniformity. It is found that the heat transfer rate of the optimized model is increased by 6.0% of that of the reference heat exchanger model, and the pressure drop by 0.4%

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2617-2620
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• 2003

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2$\^$m/) and the flow chart representing the proposed algorithm has been proposed. And also, we get the degree from the value of xm＋k formation to the value of k = 7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k = 7, one AND gate and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gates and sever Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.173-176
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• 2002

This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs the radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of the radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.125-128
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• 2002

This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs tile radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of tile radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.45-58
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• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.53-61
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• 2004

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.