• Title/Summary/Keyword: parallel machines

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Parallel Machine Scheduling with Identical Jobs and Sequence-Independent Setup Times (순서 독립적인 셋업타임을 가진 동일작업의 병렬기계 배치스케줄링)

  • Choi, Byung-Cheon;Park, Myoung-Ju
    • Journal of the Korean Operations Research and Management Science Society
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    • v.39 no.3
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    • pp.83-91
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    • 2014
  • We consider the problem of scheduling identical jobs with sequence-independent setup times on parallel machines. The objective is to minimize total completion times. We present the pseudopolynomial-time algorithm for the case with a fixed number of machines and an efficient approximation algorithm for our problem with identical setup times, which is known to be NP-hard even for the two-machine case.

Parallel Operation of Trans-Z-Source Network Full-Bridge DC-DC Converter for Wide Input Voltage Range

  • Lee, Hyeong-Min;Kim, Heung-Geun;Cha, Hon-Nyong
    • Journal of international Conference on Electrical Machines and Systems
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    • v.1 no.2
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    • pp.98-104
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    • 2012
  • This paper presents a novel transformer isolated parallel connected full-bridge dc-dc converter using recently developed trans-Z-source network. Unlike the traditional voltage -fed or current-fed converters, the proposed converter can be open- and short-circuited without damaging switching devices. Therefore, the desired buck and boost function can be achieved and the converter reliability can be greatly improved. A 6 kW prototype dc-dc converter is built and tested to verify performances of the proposed converter.

A Novel Control Strategy for Input-Parallel-Output-Series Inverter System

  • Song, Chun-Wei;Zhao, Rong-Xiang;Lin, Wang-Qing;Zeng, Zheng
    • Journal of international Conference on Electrical Machines and Systems
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    • v.1 no.2
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    • pp.85-90
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    • 2012
  • This paper presents a topology structure and control method for an input-parallel-output-series(IPOS) inverter system which is suitable for high input current, high output voltage, and high power applications. In order to ensure the normal operation of the IPOS inverter system, the control method should achieve input current sharing(ICS) and output voltage sharing(OVS) among constituent modules. Through the analysis in this paper, ICS is automatically achieved as long as OVS is controlled. The IPOS inverter system is controlled by a three-loop control system which is composed of an outer common-output voltage loop, inner current loops and voltage sharing loops. Simulation results show that this control strategy can achieve low total harmonic distortion(THD) in the system output voltage, fast dynamic response, and good output voltage sharing performance.

Parallel Multiple Electric Power Conversion System Constructed by Connecting Three Power Converters

  • Nakai, Mitsuki;Inaba, Hiromi;Kishine, Keiji;Ishikura, Keisuke
    • Journal of international Conference on Electrical Machines and Systems
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    • v.3 no.3
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    • pp.276-281
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    • 2014
  • The electric power conversion system constructed by connecting two or more power converters in parallel is an advantageous method for making to large capacity and standardization. In this paper, the control method of cross current when three power converters are operated is examined, and it reexamined a preferable system construction method.

Heuristic Procedure on Minimizing Makespan for Preemptive Sequence Dependent Job Scheduling with Parallel Identical Machines (일시(一時) 작업중단(作業中斷)을 허용(許容)하는 순서종속작업(順序從屬作業)을 병행기계(並行機械)로서 makespan 최소화(最小化)를 도모(圖謀)하는 발견적(發見的) 방법(方法))

  • Won, Jin-Hui;Kim, Man-Sik
    • Journal of Korean Institute of Industrial Engineers
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    • v.13 no.2
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    • pp.35-46
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    • 1987
  • To minimize makespan for preemptive sequence dependent job scheduling with parallel identical processors, fundamental results, as the basis of new algorithm to be presented, such as McNauton's algorithm for independent jobs, Hu's characterization for dependent jobs, and Muntz-Coffman's algorithm, were first introduced. Then a huristic procedure was presented applying those concepts of zoning of assembly line balancing and of resource leveling on CPM network scheduling with two or more of parallel machines in general. New procedure has eliminated presumative machine assignment using ${\rho}$, rate of resource capability (${\rho}$ < 1), for practical scheduling.

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A Genetic Algorithm for Minimizing Total Tardiness with Non-identical Parallel Machines (이종 병렬설비 공정의 납기지연시간 최소화를 위한 유전 알고리즘)

  • Choi, Yu-Jun
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.38 no.1
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    • pp.65-73
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    • 2015
  • This paper considers a parallel-machine scheduling problem with dedicated and common processing machines using GA (Genetic Algorithm). Non-identical setup times, processing times and order lot size are assumed for each machine. The GA is proposed to minimize the total-tardiness objective measure. In this paper, heuristic algorithms including EDD (Earliest Due-Date), SPT (Shortest Processing Time) and LPT (Longest Processing Time) are compared with GA. The effectiveness and suitability of the GA are derived and tested through computational experiments.

Scheduling for a Two-Machine, M-Parallel Flow Shop to Minimize Makesan

  • Lee, Dong Hoon;Lee, Byung Gun;Joo, Cheol Min;Lee, Woon Sik
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.23 no.56
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    • pp.9-18
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    • 2000
  • This paper considers the problem of two-machine, M-parallel flow shop scheduling to minimize makespan, and proposes a series of heuristic algorithms and a branch and bound algorithm. Two processing times of each job at two machines on each line are identical on any line. Since each flow-shop line consists of two machines, Johnson's sequence is optimal for each flow-shop line. Heuristic algorithms are developed in this paper by combining a "list scheduling" method and a "local search with global evaluation" method. Numerical experiments show that the proposed heuristics can efficiently give optimal or near-optimal schedules with high accuracy. with high accuracy.

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Implementation and Performance Evaluation of Parallel Programming Translator for High Performance Fortran (High Performance Fortran 병렬 프로그래밍 변환기의 구현 및 성능 평가)

  • Kim, Jung-Gwon;Hong, Man-Pyo;Kim, Dong-Gyu
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.4
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    • pp.901-915
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    • 1999
  • Parallel computers are known to be excellent in performance per cost also satisfying scalability and high performance. However parallel machines have enjoyed limited success because of difficulty in parallel programming and non-portability between parallel machines. Recently, researchers have sought to develop data parallel language that provides machine independent programming systems. Data parallel language such as High Performance Fortran provides a basis to write a parallel program based on a global name space by partitioning data and computation, generating message-passing function. In this paper, we describe the Parallel Programming Translator(PPTran), source-to-source data parallel compiler, generating MPI SPMD parallel program from HPF input program through four phases such as data dependence analysis, partitioning data, partitioning computation, and code generation with explicit message-passing and verify the performance of PPTran

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Speedup Analysis Model for High Speed Network based Distributed Parallel Systems (고속 네트웍 기반의 분산병렬시스템에서의 성능 향상 분석 모델)

  • 김화성
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12C
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    • pp.218-224
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    • 2001
  • The objective of Distributed Parallel Computing is to solve the computationally intensive problems, which have several types of parallelism, on a suite of high performance and parallel machines in a manner that best utilizes the capabilities of each machine. In this paper, we propose a computational model including the generalized graph representation method of distributed parallel systems for speedup analysis, and analyze how the super-linear speedup is achieved when scheduling of programs with diverse embedded parallelism modes onto a distributed heterogeneous supercomputing network environment. The proposed representation method can also be applied to simple homogeneous or heterogeneous systems whose components are heterogeneous only in terms of the processor speed. In order to obtain the core speedup, the matching of the parallelism characteristics between tasks and parallel machines should be carefully handled while minimizing the communication overhead.

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Heuristics for Line Balancing in Hybrid Flowshops (혼합 흐름공정에서 라인 밸런싱을 위한 휴리스틱 개발)

  • Lee, Geun-Cheol
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.30 no.3
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    • pp.94-102
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    • 2007
  • In this paper, we consider a line balancing problem in hybrid flowshops where each workstation has identical parallel machines. The number of machines in each workstation is determined in ways of satisfying pre-specified throughput rate of the system. To minimize the total number of machines in the systems, we propose five heuristic methods and one simulated annealing method. Extensive computational experiments found the superiorities of two heuristic methods and the meta-heuristic.