• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.240-248
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• 2014

It is DC power that Output of renewable energy being recently developed and researched. Also, demand of DC power will expect to proliferate due to increase of digital load. Thus, DC distribution system providing high quality of power and reliability has emerged as a new distribution system. If the conventional distribution systems are substituted by proposed DC distribution system, the output of renewable energy can be connected with distribution systems under minimum power conversion. Therefore, in the event of connection with DC load, it can construct an efficient distribution system. In this paper, the integrated parallel operation of power conversion module for DC distribution system is proposed. Also, this paper proposed modularization of power conversion devices for DC distribution system and power control for parallel operation of large capacity system. DC distribution system consists of three power conversion modules such as AC/DC power conversion module 2 set, ESS module 1 set. DC distribution system controls suitable operation depending on the status of the DC power distribution system and load. Integrated operation of these systems is verified by simulation and experiment results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2690-2700
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• 1997

This paper presents parallel sorting algorithm, SHARED-MEMORY-BS and REDUCED-BS, which are implemented on shared-memory parallel computers. These algorithm sort N keys in $O(log^2N)$ time. REDUCED-BS users a parity strategy which gives an idea for the efficient usage of the local memory associated with each processor. By taking advantage of the local memory associated with each processor, the communication of REDUCED-BS is decreased by approximately half that of SHARED-MEMORY-BS. On the basis of alleviating the communication, the algorithm REDUCED-BS results in a significant improvement of performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.288-294
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• 2017

Recently, deep learning using convolutional neural network (CNN) has been extensively studied in image recognition. Convolution consists of addition and multiplication. Multiplication is computationally expensive in hardware implementation, relative to addition. It is also important factor limiting a chip design in an embedded deep learning system. In this paper, I propose a parallel-addition processing algorithm that converts grayscale images to the superposition of binary images and performs convolution only with addition. It is confirmed that the convolution can be performed by a parallel-addition method capable of reducing the processing time in experiment for verifying the availability of proposed algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.27-31
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• 2017

A high-performance wideband transition from double-sided parallel-stripline (DSPSL) to coplanar stripline (CPS) is proposed. This transition is designed by consideration of gradual field transformation and optimal impedance matching between DSPSL and CPS. Clear design guidelines of proposed transition are provided to determine the ground shape and the transition length. The fabricated transition exhibits less than 0.7 dB insertion loss per transition for frequencies from 6.2 to 18.2 GHz, and less than 1.25 dB insertion loss to over 30 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.87-94
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• 2002

In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4347-4366
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• 2015

Distinguished with traditional strategies which offload an application's computation to a single server, parallel computation offloading can promote the performance by simultaneously delivering the computation to multiple computing resources around the mobile terminal. However, due to the variability of communication and computation environments, static application component multi-partitioning algorithms are difficult to maintain the optimality of their solutions in time-varying scenarios, whereas, over-frequent algorithm executions triggered by changes of environments may bring excessive algorithm costs. To this end, an adaptive application component mapping algorithm for parallel computation offloading in variable environments is proposed in this paper, which aims at minimizing computation costs and inter-resource communication costs. It can provide the terminal a suitable solution for the current environment with a low incremental algorithm cost. We represent the application component multi-partitioning problem as a graph mapping model, then convert it into a pathfinding problem. A genetic algorithm enhanced by an elite-based immigrants mechanism is designed to obtain the solution adaptively, which can dynamically adjust the precision of the solution and boost the searching speed as transmission and processing speeds change. Simulation results demonstrate that our algorithm can promote the performance efficiently, and it is superior to the traditional approaches under variable environments to a large extent.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.69-79
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• 2012

In this paper, we restrict the case as m odd, n=mk, and propose and explicitly exhibit the architecture of a new parallel multiplier over the field GF($2^m$) with a type k Gaussian period which is a subfield of the field GF($2^n$) implements multiplication using the parallel multiplier over the extension field GF($2^n$). The complexity of the time and area of our multiplier is the same as that of Reyhani-Masoleh and Hasan's multiplier which is the most efficient among the known multipliers in the case of type IV.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1196-1200
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• 2009

This paper proposed a tunable band pass filter. It is two-poles direct capacitive coupled resonator band pass filter which the capacitors of parallel resonators are changed by varactor diodes. The DC bias controls to change the value of capacitance in the parallel resonator for tunning the pass band. To validate the proposed design method, we fabricated the band pass filter which has tunable center frequency from 200MHz to 245MHz.

• ETRI Journal
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• v.38 no.6
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• pp.1042-1051
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• 2016

The mobile hotspot network (MHN), which is capable of providing a data rate of gigabits per second at high speed, is considered a potential use case of the future enhanced mobile broadband for 5G. Because a unidirectional network deployment has been considered for an MHN, non-orthogonal multiple access (NOMA) can be employed to improve the system performance. For a practical implementation of NOMA under an MHN highway scenario where multiple pieces of MHN terminal equipment are served through the same beam simultaneously, a NOMA transceiver is proposed in this paper. For the NOMA transmitter, Gray-coded QAM constellation mapping is extended to arbitrary modulation order q. For the NOMA receiver, successive interference cancellation (SIC) is no longer necessary, and instead, a parallel demodulation is proposed. The numerical and simulation results suggest that the proposed NOMA transceiver outperforms the conventional NOMA SIC receiver and can be flexibly used for an MHN highway scenario.