• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1014-1017
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• 2006

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for $ITO/Alq_3/LiF/Al$ device structure. The admittance spectroscopic analysis of the devices with LiF layer shows reduction in contact resistance $(R_C)$, parallel resistance $(R_P)$ and increment in parallel capacitance $(C_P)$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1070-1073
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• 2002

This study presents a parallel branch-and-bound (PBAB) method for traveling salesman problem (TSP). The PBAB method adopts intermediate form of central control and distributed control in terms of the lightness of the master process's role. Compared with fully distributed control, the control scheme involves less concentration of communication on the master. Moreover, in order to reduce the influence of communication, the worker is composed of a computation thread and a communication thread. The multithreadness realizes the almost blocking free communications on the master. We implement the proposed PBAB method on a network of PCs, which consists of one master and up to 16 workers. We experiment five TSP instances. The results shows that the efficiency increases with the problem size.

• ETRI Journal
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• 제39권5호
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Journal of information and communication convergence engineering
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• 제19권3호
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• pp.155-160
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• 2021

Differential evolution is an efficient algorithm for solving continuous optimization problems. However, its performance deteriorates rapidly, and the runtime increases exponentially when differential evolution is applied for solving large-scale optimization problems. Hence, a novel cooperative coevolution differential evolution based on Spark (known as SparkDECC) is proposed. The divide-and-conquer strategy is used in SparkDECC. First, the large-scale problem is decomposed into several low-dimensional subproblems using the random grouping strategy. Subsequently, each subproblem can be addressed in a parallel manner by exploiting the parallel computation capability of the resilient distributed datasets model in Spark. Finally, the optimal solution of the entire problem is obtained using the cooperation mechanism. The experimental results on 13 high-benchmark functions show that the new algorithm performs well in terms of speedup and scalability. The effectiveness and applicability of the proposed algorithm are verified.

• 한국정보과학회논문지:시스템및이론
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• 제29권10호
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• pp.539-549
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• 2002

PC클러스터 기반 정보 검색 시스템은 질의를 클러스터 상의 노드에 분산시켜 병렬로 처리함으로써 전체 시스템의 성능을 향상시킬 수 있다. 그러나, 노드 사이의 데이터 교환을 위하여 TCP/IP 기반 통신을 사용하는 것은 전체 시스템 성능 저하의 원인이 된다. 이를 해결하기 위해 개발된 것이 사용자 수준 통신(user-level communication)이다. 이것은 성능에 치명적인 영향을 미치는 커널 접근을 통신 단계에서 제거함으로써 적은 지연시간과 높은 대역폭을 제공한다. 본 논문에서는 사용자 수준 통신 방법의 업계 표준인 VIA(Virtual Interface Architecture)를 기반으로 한 효율적인 병렬 정보 검색 시스템을 제안한다. 본 논문의 정보 검색 시스템은 SCI(Scalable Coherent Interface) 기반의 VIA 방식, SCI 기반의 VIA/MPI 방식 그리고 Fast Ethernet 기반의 VIA/MPI 방식으로 구현되었으며 실험을 통하여 세 방식의 성능을 비교 분석하였다.

• Journal of Information Processing Systems
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• 제4권4호
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• 한국정보통신학회논문지
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• 제21권6호
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• pp.1113-1120
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• 2017

최근 정보통신 기술의 발달로 인하여 데이터의 양이 점차 증가하고 있으며, 이에 대한 처리와 관련된 연구가 활발히 진행되고 있다. 주어진 집합 내에 특정 개체의 존재여부를 알기위해 사용되고 있는 블룸필터는 데이터의 공간 활용에 매우 유용한 구조이다. 본 논문에서는 블룸필터의 긍정오류확률에 대한 요인분석과 함께, 긍정오류를 최소화 시키기 위한 방안으로 병렬구조 방식의 블룸필터를 제안한다. 일반 블룸필터의 최소 긍정오류확률값을 가질 수 있도록 구현된 병렬 불룸필터 방식은 일반 블룸필터 크기의 메모리와 유사한 크기를 사용하지만, 해쉬함수별로 병렬 처리함으로서, 속도를 높일 수 있다는 장점을 가진다. 또한 완전 해쉬함수를 사용하는 경우에는 삽입뿐 아니라, 삭제도 가능하다는 장점을 가진다.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.128-133
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• 2006

본 논문에서는 고속 통신용 인터페이스 회로를 RMVL(redundant multi-valued logic)을 이용하여 CMOS 회로로 설계하였다 설계한 1:4 디멀티플렉서 (demuitiplexer, serial-parallel convertor)는 직렬 데이터를 병렬 redundant 다치 데이터로 변환하는 부호화 회로와 redundant 다치 데이터를 병렬 이진 데이터로 변환하는 복호화 회로로 구성된다. 이 회로는 0.35um 표준 CMOS 공정을 이용하여 구현하였으며, 기존의 이진 논리회로보다 고속 동작을 한다. 이 회로는 3.3V의 공급전원에서 4.5Gb/s 이상의 동작속도와 53mW의 전력소모를 가지며, 동작속도는 0.35um 공정이 가지는 최대 주파수에 의해 제한된다. 설계한 회로가 높은 동작 주파수를 가지는 미세공정상에서 사용될 경우 100b/s 이상의 고속 통신용 인터페이스 구현이 가능하다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권6호
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• 한국정보통신학회논문지
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• 제17권12호
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• pp.2921-2926
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• 2013

본 논문에서 제안된 십진 부동소수점 연산 장치(decimal floating-point arithmetic unit, DFP)는 L.K.Wang에 의해 제안된 십진 부동소수점 유닛을 기반으로 하여 데이터의 병렬 처리를 통해 동일한 크기의 지수를 갖는 두 오퍼랜드의 가수 영역의 고속 연산을 지원하도록 재설계 하였다. 제안된 십진 부동소수점 연산 장치는 Xilinx ISE를 이용하여 xc2vp30-7ff896 타겟 디바이스로 합성하였으며 (주)시스템센트로이드의 Flowrian을 통해 시뮬레이션 검증하였다. 제안된 방식은 L.K.Wang에 의해 제안된 설계 방식 및 참고문헌 [6]의 설계 방식과 비교하여 동일한 입력 데이터를 이용하여 시뮬레이션 검증한 결과, L.K.Wang 방식보다 약 8.4%, 참고문헌 [6]의 방식보다 약 3% 정도의 처리 속도가 향상되었다.