• Title/Summary/Keyword: package method

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Design of the Real Time Disparity System using Vertical Strip Structure (수직축 Strip구조를 이용한 실시간 Disparity시스템의 설계)

  • 강봉순;양훈기
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.4
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    • pp.91-100
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    • 2004
  • In this paper, we propose the method that analyzes the depth of object using 2 images in the disparity algorithm. It also presents the design and implementation of the proposed method for a real time processing. The proposed system uses the vertical strip structure for calculating similar pixel numbers for the processing and converts the depth of object into gray scale images in order to be displayed on various display devices. The hardware using the proposed method is operating with 30 frames/sec and verified by using the Altera APEX 20K1000EBC652-3. The proposed method is also Implemented into It by using the Hynix 0.35${\mu}{\textrm}{m}$ CB35 ASIC library and 256PQFP package.

Low-Cost Hologram Module for Optical Pickup by Adjusting Photodiode Package (포토 다이오드 조정방식을 이용한 광 픽업용 저가 홀로그램 모듈)

  • Jeong, Ho-Seop;Kyong, Chon-Su
    • Korean Journal of Optics and Photonics
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    • v.16 no.4
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    • pp.345-353
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    • 2005
  • We proposed a new and cost-effective method fer assembling holographic pickup modules without any high resolution vision system. Assembling was accomplished by adjusting photodiode package only, leading to a low cost, holographic pickup module. Focus and tracking error signals were simply determined by comparing spot sizes and by using the 3 beam method, respectively, based on four-sectional holographic optical elements. In experiment, we assembled a hologram module and estimated performance of the proposed method fur a holographic pickup module used in compact disc system.

Stress Analysis and Lead Pin Shape Design in PGA (Pin Grid Array) Package (PGA (Pin Grid Array) 패키지의 응력해석 및 Lead Pin 형상설계)

  • Cho, Seung-Hyun;Choi, Jin-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.2
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    • pp.29-33
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    • 2011
  • Research about the geometry design of lead pin was carried based on the normal or shear stress of the interface between a lead pin and a PCB in terms of delamination failure. The taguchi method with four design factors of three levels and FEA(Finite element Analysis) are carried under $20^{\circ}$ bending and 50 ${\mu}m$ tension of lead pin. The contact width, d2, between head round and copper pad in PCB is the highest affection factor among design factors by analysis of contribution analysis. Equivalent von Mises stress of 18.7% reduction design is obtained by the parameter design of the taguchi method. Maximum normal stress occurred at contact position between solder outer surface and a Cu pad in PCB. Also, maximum shear stress happened at contact position between solder outer surface and SR layer of PCB. From these calculated results, delamination of the PGA package may be occurred from outer interface of solder to inner interface of solder.

Finite Element Analysis on Process Improvement of the Multi-Forming for the Motor-Case of an Automobile (자동차용 모터케이스 성형용 멀티포머의 공정개선에 관한 유한요소해석)

  • Kim H. J.;Bae W. B.;Cho J. R.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 2005.05a
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    • pp.467-470
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    • 2005
  • There are about 10 motors for tile actuator of the automation system in an auto-mobile recently. The performance of the motor-case is much related to the noise and the vibration of an auto-mobile Multi-Forming process is so much the better than existing deep-drawing or Multi-step forming by press by less cost, installation and staff. But there isn't the specific and general process design, so we aren't good at competition. So in the first step, I want to study about the core design for the multi-forming process. We can access by the elasto-plastic theory and the finite element method, and we use a commercial package of the Deform-2D and, Deform-3D which is based on three-dimensional elasto-plastic finite element, evaluated propriety oi the package. The evaluation of the package propriety was simulated by simple bending example. It was found the elasto-plastic theory was mostly in agreement with the simulation. We proposed that three type of section for the core and analyzed by finite element method (Deform-2D). We can get the best result with the ellipse type core. Then we apply the result of the preceding analysis to the finite element method (Deform-3D). In 3D-finite element analysis, we can get the result of 8/100mm-roundness. This result can help the improvement of the multi-forming process.

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On-Chip Process and Characterization of the Hermetic MEMS Packaging Using a Closed AuSn Solder-Loop (사각고리형상의 AuSn 합금박막을 이용한 MEMS 밀봉 패키징 및 특성 시험)

  • Seo, Young-Ho;Kim, Seong-A;Cho, Young-Ho;Kim, Geun-Ho;Bu, Jong-Uk
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.28 no.4
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    • pp.435-442
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    • 2004
  • This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

Development of Ultra-compact LED Package and Analysis of Defect Type (극소형 LED 패키지의 개발과 불량 유형의 분석)

  • Lee, Jong Chan
    • Journal of the Korea Convergence Society
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    • v.8 no.12
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    • pp.23-29
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    • 2017
  • This paper introduces the mold technology for the development of ultra-compact package of less than 1mm, and also analyze the error pattern of the results using this mold technology. The existing ultra-small mold structure was one-piece, which caused the surface of EDM to be rough and increase the error rate. This has been an obstacle to further reducing the size of the mold. On the other hand, the proposed mold technology tries to overcome the limitation of the one-piece type by using the prefabricated type method. This paper also classify defect patterns in the results of the proposed mold structure and analyze the occurrence probability of each pattern to use as a basic data to develop a detector.

A Driver Space Design of Passenger Vehicle using Forward Kinematics Model (Forward Kinematics 모델을 이용한 자동차 운전공간의 설계)

  • Jeong, Seong-Jae;Park, Min-Yong
    • Journal of the Ergonomics Society of Korea
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    • v.21 no.2
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    • pp.47-58
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    • 2002
  • This research suggested the mathematical model (forward kinematics method) to provide the reference points of driver space more easily and accurately in designing the package layout of vehicle interiors. For this purpose, the lengths of body segments of drivers and various joint angles occurred while were used. The length data between joints for the mathematical model were extracted from $SAFEWORK^{\circed{R}}$ as well as 95th percentile male and 5th percentile female body dimensions were utilized. In addition, the angles of body segments were applied on its diverse values within proper ranges in order to compare them each other. the mathematical model in this study was based on the concept of converting polar coordinate system to Cartesian coordinate system so that reference points of driver space were acquired in Cartesian coordinate system after using the segment lengths of drivers and the joint angles of driving postures as an input of polar coordinate system. It is expected that reference points of driver space obtained from this research are helpful to the study on package layout that is appropriate for physical characteristics of drivers.

Definition of an Integrated Contract Package for Application of Multi-Trade Subcontract System (다공종 통합발주방식 적용을 위한 통합공종 규명에 관한 연구)

  • Song Hyung-Suk;Kim Kyoon-Tai;Han Choong-Hee;Kim Sun-Kuk
    • Proceedings of the Korean Institute Of Construction Engineering and Management
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    • autumn
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    • pp.385-388
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    • 2002
  • The construction industry has complicated production processes with diverse disciplines and subcontractors, which is the major cause of lowered productivity. To solve this problem, multi-trade subcontract system is recently suggested. Some general construction companies have applied this method to some sections of work process. However, this is in the early stage of application. The purpose of this study is to define an integrated contract package for improving both contractor and subcontractor efficiency. First, this study recognizes construction company to need of multi-trade subcontract system. Finally, it suggests feasible activities which can be useful for a construction company to apply to this subcontract system.

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The Thermal Fatigue Analysis and Life Evaluation of Solder Joint for Flip Chip Package using Darveaux Model (Darveaux 모델에 의한 플립칩 패키지 솔더 접합부의 열피로 해석 및 수명 평가)

  • Shin Young-Eui;Kim Yeon-Sung;Kim Jong-Min;Choi Myun-Gi
    • Journal of Welding and Joining
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    • v.22 no.6
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    • pp.36-42
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    • 2004
  • Experimental and numerical approaches on the thermal fatigue for the solder joint of flip chip package are discussed. However, it is one of the most difficult problems to choose the proper fatigue model. It was found that viscoplstic FE model with Darveaux method was very desirable and useful to predict the thermal fatigue life of solder joint for flip chip package under $208{\~}423K$ thermal cycling condition such as steep slope of temperature(JEDEC standard condition C). Thermal fatigue life was 1075 cycles as a result of viscoplatic model. It was a good agreement compared to the experimental. And also, it was found from the experimental that probability of the thermal fatigue life was $60{\%}$ at 1500 cycles.

Wafer Level Package Using Glass Cap and Wafer with Groove-Shaped Via (유리 기판과 패인 홈 모양의 홀을 갖는 웨이퍼를 이용한 웨이퍼 레벨 패키지)

  • Lee, Joo-Ho;Park, Hae-Seok;Shin, Jea-Sik;Kwon, Jong-Oh;Shin, Kwang-Jae;Song, In-Sang;Lee, Sang-Hun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2217-2220
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    • 2007
  • In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.