• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.708-712
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• 2004

Shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes. The dopant implantation was performed into the crystalline substrates using BF$_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth and sheet resistance. A new simulator is designed to model boron diffusion in silicon. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using initial conditions and boundary conditions, coupled diffusion equations are solved successfully. The simulator reproduced experimental data successfully.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• 한국전기전자재료학회논문지
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• 제30권6호
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• pp.372-375
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• 2017

ZnO thin films were deposited by RF magnetron sputtering and then diffused by using an As source in the ampouletube. Also, the ZnO p-n homojunction was made by using As-doped ZnO thin films, and its properties were analyzed. After the As doping, the surface roughness increased, the crystal quality deteriorated, and the full width at half maximum was increased. The As-doped ZnO thin films showed typical p-type properties, and their resistivity was as low as $2.19{\times}10^{-3}{\Omega}cm$, probably because of the in-diffusion from an external As source and out-diffusion from the GaAs substrate. Also, the ZnO p-n junction displayed the typical rectification properties of a p-n junction. Therefore, the As diffusion method is effective for obtaining ZnO films with p-type properties.

• 대한전자공학회논문지SD
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• 제42권10호
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• pp.9-18
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• 2005

Si, GaAs, InP 및 $In_{0.53}Ga_{0.47}AS$ 계단형 $p^{+}n$ 접합에서의 항복전압을 위한 해석적 표현식을 유도하였다. 해석적 항복전압을 위해 각 물질에 대한 Marsland의 lucky drift 파라미터를 이용하여 유효이온화계수를 각각 추출하였고, 이의 이온화 적분을 통해 얻은 해석적 항복전압 결과는 $10^{14}cm\;^{-3}\~5\times10\;^{17}cm\;^{-3}$도핑 농도 범위에서 실험 결과와 $10\%$ 오차 범위 이내로 잘 일치하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.315.1-315.1
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• 2014

The use of cellulose papers has recently attracted much attention in various device applications owing to their natural advantageous properties of earth's abundance, bio-friendly, large-scale production, and flexibility. Conventional metal oxides with novel structures of nanorods, nanospindles, nanowires and nanobelts are being developed for emerging electronic and chemical sensing applications. In this work, both ZnO (n-type) nanorod arrays (NRAs) and CuO (p-type) nanospindles (NSs) were synthesized on cellulose papers and the p-n junction property was investigated using the electrode of indium tin oxide coated polyethylene terephthalate film. To synthesize ZnO and CuO nanostructures on cellulose paper, a simple and facile hydrothermal method was utilized. First, the CuO NSs were synthesized on cellulose paper by a simple soaking process, yielding the well adhered CuO NSs on cellulose paper. After that, the ZnO NRAs were grown on CuO NSs/cellulose paper via a facile hydrothermal route. The as-grown ZnO/CuO NSs on cellulose paper exhibited good crystalline and optical properties. The fabricated p-n junction device showed the I-V characteristics with a rectifying behaviour.

• 한국재료학회지
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• 제6권7호
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• pp.678-683
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• 1996

In the fabrication processes of thin film thermoelectrics, a subsequent annealing treatment is inevitable to reduce the defects and residual stresses introduced during the film growth, and to make the uniform carrier concentration of the film. However, the diffusion-induced atomic redistribution and the broadening of p/n junction region are expected to affect the thermoelectric properties of thin film modules. The present study intends to investigate the diffusion at the p/n junctions of thermoelectric thin films and to relate it to the property changes. The film junctions of p-type(Bi0.5Sb1.5Te3)and n-type(Bi2Te2.4Se0.6)were prepared by the flash evaporation method. Aluminum thin layer was employed as a diffusion barrier between p-and n-type films of the junction. This was found to be an effective barrier by showing a negligible diffusion into both type films. After annealing treatment, the thermoelectric properties of p/n couples with aluminum barrier layer were accordingly retained their properties without any deterioration.

• Transactions on Electrical and Electronic Materials
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• 제3권2호
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• pp.10-15
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• 2002

In this paper, the electrical characteristics of fabricated p+-n junction diode are demonstrated and interpreted with different theoretical calculations. Dopants distribution by boron ion implantation on silicon wafer were simulated with TRIM-code and ICECaEM simulator. In order to make electrical activation of implanted carriers, thermal annealing treatments are carried out by RTP method for 1min. at $1000^{circ}C$ under inert $N_2$ gas condition. In this case, profiles of dopants distribution before and after heat treatments in the substrate are observed from computer simulations. In the I-V characteristics of fabricated diodes, an analytical description method of a new triangular junction model is demonstrated and the results with calculated triangular junction are compared with measured data and theoretical calculated results of abrupt junction. Forward voltage drop with new triangular junction model is lower than the case of abrupt junction model. In the C-V characteristics of diode, the calculated data are compared with the measured data. Another I-V characteristics of diodes are measured after proton implantation in electrical isolation method instead of conventional etching method. From the measured data, the turn-on characteristics after proton implantation is more improved than before proton implantation. Also the C-V characteristics of diode are compared with the measured data before proton implantation. From the results of measured data, reasonable deviations are showed. But the C-V characteristics of diode after proton implantation are deviated greatly from the calculated data because of leakage currents in defect regions and layer shift of depletion by proton implantation.

• 한국진공학회지
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• 제6권4호
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• pp.326-336
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• 1997

트랜지스터의 소오스/드레인 접합 특성에 가장 큰 영향을 미치는 인자는 이온 주입 시 발생한 실리콘 내에 발생한 결합이라는 사실에 착안하여, 기존 소오스/드레인 접합 형성 공정과 다른 새로운 방식을 도입하여 이온 주입에 의해 생긴 결함의 제어를 통해 고품질 초 저접합 $p^+$-n접합을 형성하였다. 기존의 $p^+$소오스/드레인 접합 형성 공정은 $^{49}BF_2^+$ 이온 주입 후 층간 절연막들인 TEOS(Tetra-Ethyl-Ortho-Silicate)막과 BPSG(Boro-Phospho-Silicate-Glass)막을 증착 후 BPSG막 평탄화를 위한 furnace annealing 공정으로 진행된다. 본 연구에서는 이러한 기존 공정과는 달리 층간 절연막 증착 전 저온 RTA첨가 방법, $^{49}BF_2^+$와 $^{11}B^+$ 을 혼합하여 이온 주입하는 방법, 그리고 이온 주입 후 잔류 산화막을 제거하고 MTO(Medium temperature CVD oxide)를 증착하는 방법을 제시하 였으며, 각각의 방법은 모두 이온 주입에 의한 실리콘 내 결합 농도를 줄여 기존의 방법보 다 더 우수한 양질의 초 저접합을 형성할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.286-289
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• 2003

In the case of high voltage devices, junction termination plays an important role in determining the breakdown voltage of the device. The mesa junction termination has been demonstrated to yield nearly ideal breakdown voltage for 6H-SiC p-n junctions. However, such an approach may not be attractive because of the nonplanar surface, which is difficult to passivate. Moreover, In case of 4H-SiC, ideal breakdown voltage could not be achieved using mesa junction termination. For 4H-SiC planar junction termination technique is more useful one rather than mesa junction termination. In this paper, breakdown characteristics of the 4H-SiC device with planar junction termination, such as FLR(Field Limiting Ring), FP(Field Plate) and JTE(Junction Termination Extension), is presented. In the case of the FLR, breakdown voltage of 1800V is obtained. And breakdown voltage of 1000V and 1150V is also obtained for the case of FP and JTE case, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.195-196
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• 2009

This paper describes the fabrication and characteristics of polycrystalline 3C-SiC thin film diodes for extreme environment applications, in which the this thin film was deposited onto oxidized Si wafers by APCVD using HMDS In this work, the optimized growth temperature and HMDS flow rate were $1,100^{\circ}C$ and 8sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/$SiO_2$/Si(n-type) structure was fabricated and its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) values were measured as 0.84V, over 140V, 61nm, and $2.7{\times}10^{19}cm^2$, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and $500^{\circ}C$ for 30min under a vacuum of $5.0{\times}10^{-6}$Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.