• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.495-499
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• 2004

Characteristics of ohmic Ni/Si/Ni contacts to n-type 4H-SiC are investigated systematically. The ohmic contacts were formed by annealing Ni/Si/Ni sputtered sequentially The annealings were performed at 950℃ using RTP in vacuum ambient and N₂ ambient, respectively. The specific contact resistivity(p/sub c/), sheet resistance(R/sub s/), contact resistance (R/sub c/) transfer length(L/sub T/) were calculated from resistance(R/sub T/) versus contact spacing(d) measurements obtained from TLM(transmission line method) structure. While the resulting measurement values of sample annealed at vacuum ambient were p/sub c/ = 3.8×10/sup -5/Ω㎠, R/sub c/ = 4.9 Ω and R/sub T/ = 9.8 Ω, those of sample annealed at N₂ ambient were p/sub c/ = 2.29×10/sup -4/Ω㎠, R/sub c/ = 12.9 Ω and R/sub T/ = 25.8 Ω. The physical properties of contacts were examined using XRD 3nd AES. The results showed that nickel silicide was formed on SiC and Ni was migrated into SiC. This result indicates that Ni/Si/Ni ohmic contact would be useful in high performance electronic devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.236-236
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• 2010

단일접합 $n^+-p/p^+$ (p-emitter) 및 $p^+-n/n^+$ (n-emitter) GaAs 태양전지 (Solar Cell)를 각각 제작하여, 그 소자특성을 비교 분석하였다. AM 1.5 (1 sun, $100\;mW/cm^2$) 표준광을 조사할 경우, p-emitter/n-emitter 소자의 개방회로전압 (Voc), 단락회로전류 (Jsc), 충전율 (FF), 효율 (Eff)은 각각 0.910/0.917 V, $15.9/16.1\;mA/cm^2$, 78.7/78.9, 11.4/12.1%로서, n-emitter 소자가 다소 크지만 거의 비슷한 값을 가지고 있었다. 태양전지의 집광 특성을 분석하기 위하여 조사광의 출력에 따른 태양전지의 소자 특성을 측정하였다. 조사광 강도가 높아짐에 따라 p-emitter 소자의 특성은 점진적으로 증가하는 반면, n-emitter는 1.3 sun에서 약 1.4 배의 최대 효율 (17%)을 나타내고 조사광이 더 증가함에 따라 급격히 감소하는 특성을 보여 주었다. (그림 참고) 본 연구에서 사용한 2종류 소자의 층구조는 서로 반대되는 대칭구조로서, 모두 가까이에 위치하고 있는 표면전극 (surface finger) 방향으로 소수전하 (minority carrier)가 이동하고 다수전하 (majority carrier)는 기판 (두께 $350\;{\mu}m$)을 통한 먼 거리의 후면전극 (back electrode)으로 표류 (drift)되도록 설계되어 있다. 이때, n-emitter에서는 이동도 (mobility)와 확산길이 (diffusion length)가 높은 전자가 후면전극으로 이동하기 때문에 적정밀도의 전자-정공 쌍 (EHP)이 여기될 경우에는 Jsc와 Eff가 극대화되지만, 조사광 강도 또는 EHP가 더 높아질 경우에는 직렬저항의 증가와 함께 전류-전압 (I-V)의 이상인자 (ideality factor)가 커짐으로서 FF와 효율이 급격히 감소한 결과로 분석된다. 현재 전산모사를 통한 자세한 분석을 진행하고 있으며, 본 결과는 효율 극대화를 위한 최적 층구조 및 도핑 밀도 설계에 활용할 수 있을 것으로 판단된다.

• Electrical & Electronic Materials
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• v.8 no.4
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• pp.406-412
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• 1995

A n-CdS thin films were evaporated by thermal evaporation method and their structure, optical transmission spectra and electrical characteristics were investigated. The photovoltaic characteristics of solar cells which were fabricated in optimum conditions measured. The evaporated CdS thin films showed in hexagonal structure and above 80% of optical transmission spectra regardless of impurity doping. The high quality thin films could be obtained at 150.deg. C temperature of substrate, which is useful for solar cell window layer with low resistivity of 6*10$\^$-2/(.ohm.-cm) by In doping We measured the electrical and optical characteristics of the n-CdS/p-InP heterojunction solar cells. The most efficient photovoltaic characteristics of heterojunction solar cells had the open circuit voltage of 0.66V, short circuit current density of 13.85mA/cm$\^$2/, fill factor of 0.576 and conversion efficiency of 8.78% under 60mW/cm$\^$2/ illumination.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.3
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• pp.22-26
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• 1974

The effects of anisotropic mechanical stress applied normal to the surface of p-n junctions have been investigated. As the stress increased, the breakdown voltage was decreased and the breakdown mode became softer. Within a certain limitation in the applied stress, the above phenomena werw reversibbe, though relaxation and hysteresis phenomena were observed. The time constant of relaxation depended upon the shape of the stressing tip, but for the given tip and device a unique time constant was obtained. The stress.dependence of breakdown voltage showed a good linearity up to about 3.0${\times}10^4$ kgw/$\textrm{cm}^2$, when the flat tip of radius 15$\mu$ was used, and the temperatere-dependence of breakdown voltage under the stress also showed a good linearity in the temperature range of 100 to $300^{\circ}K$.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.47-53
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• 2007

Ultra thin Si p-n junctions shallower than $300{\AA}$ were fabricated and biased to the avalanche regime. The ultra thin junctions were fabricated to be parallel to the surface and exposed to the surface without $SiO_2$ layer. Those junctions emitted white light and electrons when junctions were biased in the avalanche breakdown regime. Therefore, we could observe the avalanche breakdown region visually. We could also observe the influence of electric field to the current flow visually by observing the white light which correspond to the avalanche breakdown region. Arrayed diodes emit light and electrons uniformly at the diode area. But, the reverse leakage current were larger than those of ordinary diodes, and the breakdown voltage were less than 10V.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.3
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• pp.386-392
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• 1996

Zinc-Borosilicate is used as a side insulator wall to make high breakdown voltage with one Field Limiting Ring in a power p-n junction device in simulation. It is known that surface charge density can be yield at the interface of Zinc-Borosilicate glass / silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage is improved 1090 V under the same structure.The breakdown voltage under varying the surface charge density has a limit value. When the epitaxial thickness is varied, the position of FLR doesn't influence to the breakdown characteristic not only under non punch-through structure but also under punch-through structure. (author). 7 refs., 12 figs., 2 tabs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.242-245
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• 1997

Co single layer and Co/Ti used to form a CoSi$_2$ contact. We fabricated the n+/p diodes with this CoSi$_2$ contact as diffusion source of As. The diodes wish CoSi$_2$ formed by Co/ri bilayer had more Bo7d electrical characteristics than CoSi$_2$ formed by Co single layer. This shows that the flatness of interface which is a parameters to affect the diodes\` electrical characteristics. And the electrical characteristics of diodes are more good when the second thermal activation processing temperature was low as much as 50$0^{\circ}C$ than the temperature high over than 80$0^{\circ}C$, it was thought as that the silicide was degradated at high temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.708-712
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• 2004

Shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes. The dopant implantation was performed into the crystalline substrates using BF$_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth and sheet resistance. A new simulator is designed to model boron diffusion in silicon. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using initial conditions and boundary conditions, coupled diffusion equations are solved successfully. The simulator reproduced experimental data successfully.