• ETRI Journal
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• 제36권5호
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
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• pp.105-110
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• 2011

The doping procedure in crystalline silicon solar cell fabrication usually contains oxygen injection during drive-in process and removal of phosphorous silicate glass(PSG). In this paper, we studied the effect of oxygen injection and PSG on conversion efficiency of solar cell. The mono crystalline silicon wafers with $156{\times}156mm^2$, $200{\mu}m$, $0.5-3.0{\Omega}{\cdot}cm$ and p-type were used. After etching $7{\mu}m$ of the surface to form the pyramidal structure, the P(phosphorous) was injected into silicon wafer using diffusion furnace to make the emitter layer. After then, the silicon nitride was deposited by the PECVD with 80 nm thickness and 2.1 refractive index. The silver and aluminium electrodes for front and back sheet, respectively, were formed by screen-printing method, followed by firing in 400-425-450-550-$880^{\circ}C$ five-zone temperature conditions to make the ohmic contact. Solar cells with four different types were fabricated with/without oxygen injection and PSG removal. Solar cell that injected oxygen during the drive-in process and removed PSG after doping process showed the 17.9 % conversion efficiency which is best in this study. This solar cells showed $35.5mA/cm^2$ of the current density, 632 mV of the open circuit voltage and 79.5 % of the fill factor.

• 한국초전도ㆍ저온공학회논문지
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• 제20권4호
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• pp.41-45
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• 2018

We have investigated the effect of $Y_2O_3$ nanoparticles on the pinning properties of $Y_2O_3$-doped $GdBa_2Cu_3O_{7-{\delta}}$ (GdBCO) films. Both undoped and $Y_2O_3$-doped GdBCO films were grown on $CeO_2$-buffered MgO (100) single crystal substrates by pulsed laser deposition (PLD) using KrF (${\lambda}=248nm$) laser. The $Y_2O_3$ doping contents were controlled up to ~ 2.5 area% by varying the internal angles of $Y_2O_3$ sectors put on the top surface of GdBCO target. Compared with the $Gd_2O_3$-doped GdBCO films previously reported by our group [1], the $Y_2O_3$-doped GdBCO films exhibited less severe critical temperature ($T_c$) drop and thus slightly enhanced critical current densities ($J_c$) and pinning force densities ($F_p$) at 65 K for the applied field parallel to the c-axis of the GdBCO matrix (B//c) with increasing the doping content. Below 40 K, the in-field $J_c$ and $F_p$ values of all $Y_2O_3$-doped GdBCO films exhibited higher than those of undoped GdBCO film, suggesting that $Y_2O_3$ inclusions might act as effective pinning centers.

• 대한전자공학회논문지
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• 제21권1호
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• pp.62-70
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• 1984

비저항이 10Ω-cm, 두께가 13∼15mi1인 <111> oriented, p형 Si기판을 이용하여 N+PP+ BSF 전지와 에미터 영역이 N+N 고저 접합으로 이루어진 N+NPP+ HELEBSF(high low emitter bach surface field) 전지를 설계 제작하였다. 접합형 태양전지의 에미터 영역에서 고저 접합구조가 효율 개선에 미치는 영향을 검토하기 위해 HLEBSF 전지의 N영역을 제외하고는 같은 마스크와 동시 공정을 통해 N+PP-전지와 N+NPP+ 전지의 가영역에서 물리적 파라미터들(불순물 농도, 두께)을 동일하게 만들었다. 100mW/㎠의 인공조명에서 측정한 결과 N+PP+ 전지들의 전면적 (유효 수광면적) 평균 변환효율이 10.94%(12.16%)이었고, N+NPP+ 전지들의 평균 변환효율은 12.07% (13.41%)로 나타났다. N+NPP+ 전지의 효율개선은 N+N-고저 접합 에미터 구조가 N+ 에미터 영역에서 나타나는 heavy doping effects를 제거함으로써 에미터 재결합 전류의 증가를 억제하고 나아가 개방전압(Voc)과 단락전류(Ish)의 값을 증가시켜 준 결과로 볼 수 있다.

• 한국물환경학회지
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• 제26권6호
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• pp.963-968
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• 2010

This study has carried out to evaluate the performance of direct and indirect oxidation electrode for the purpose of decolorization of Rhodamine B (RhB) in water. Four kinds of electrodes were used for comparison: Pt and JP202 (indirect oxidation electrode), Pb and boron doping diamond (BDD, direct oxidation electrode). The effect of applied current (0.5 ~ 2.5 A), electrolyte type (NaCl, KCl, HCl, $Na_2SO_4$ and $H_2SO_4$) and electrolyte concentration (0.5 ~ 2.5 g/L), solution pH (3 ~ 11) and initial RhB concentration (25 ~ 125 mg/L) were evaluated. Experimental results showed that RhB removal efficiency were increased with increase of current, NaCl dosage and decrease of the pH. However, the effect of operating parameter on the RhB removal were different with the electrode type. JP202 electrode was the best electrode from the point of view of performance and energy consumption. The order of removed RhB concentration per energy lie in: JP202>Pt>Pb>BDD.

• 전자공학회논문지A
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• 제30A권6호
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.152-153
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• 1994

A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.