• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.505-508
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• 2006

Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.223-224
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• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1199-1202
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• 2008

High mobility bottom gate thin film transistors (TFTs) with an amorphous gallium tin zinc oxide (a-GSZO) channel layer have been produced by rf magnetron cosputtering using a gallium zinc oxide (GZO) and tin (Sn) targets. The effect of the post annealing temperatures ($200^{\circ}C$, $250^{\circ}C$ and $300^{\circ}C$) was evaluated and compared with two series of TFTs produced at room temperature and $150^{\circ}C$ during the channel deposition. From the results it was observed that the effect of pos annealing is crucial for both series of TFTs either for stability as well as for improving the electrical characteristics. The a-GSZO TFTs operate in the enhancement mode (n-type), present a high saturation mobility of $24.6\;cm^2/Vs$, a subthreshold gate swing voltage of 0.38 V/decade, a turn-on voltage of -0.5 V, a threshold voltage of 4.6 V and an $I_{ON}/I_{OFF}$ ratio of $8{\times}10^7$, satisfying all the requirements to be used in active-matrix backplane.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.38-45
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• 1989

We have studied the electrical characteristics of the hydrogenated amorphous silicon (a-Si:H) ambiploar thin film transistors (TET'S)using 100ppm boron-doped a-Si:H as an active layer. The enhancement of drain current due to the double injection behavior has been observed in the p-channel operation of the TFT. The drain current decreases with time in streched exponential form when the gate voltage is positive. The result indicates that the dangling bonds created by electron accumulation show identical time dependence as the diffusion of hydrogen in the film. We observed the experimental evidence that the doping efficiency changes either when the gate bias is applied or when the light is illuminated on boron-doped a-Si:H.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.500-500
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• 2011

With recent advances in flexible and stretchable electronics, the development of physically responsive field-effect transistors (physi-FETs) that are easily integrated with transformable substrates may enable the omnipresence of physical sensing devices in electronic gadgets. However, physical stimuli typically induce whole sensing physi-FET devices under global influences that also cause changes in the parameters of FET transducers, such as channel mobility and dielectric capacitance that prevent proper interpretations of response in sensing materials. Extended-gate structures with isolated stimuli have been used recently in physi-FETs to demonstrate performances of sensing materials only. However, such approaches are limited to prototype researches since isolated stimuli rarely occur in real-life applications. In this report, we theoretically and experimentally demonstrated that integrating piezoelectric nanocomposites directly into flexible organic FETs (OFETs) as gate dielectrics provides a general research direction to physi-FETs with a simple device structure and the capability of precisely investigating functional materials. Measurements with static stimulations, which cannot be performed in conventional systems, exhibited giant-positive d33 values of nanocomposites of barium titanate (BT) NPs and poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)).

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.324-327
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• 2020

The impact of output conductance (g_o) on the short-circuit current-gain cut-off frequency (f_T) in In_0.8Ga_0.2As high-electron-mobility transistors (HEMTs) on an InP substrate was investigated. An attempted was made to extract the values of f_T in a simplified small-signal model (SSM) of the HEMTs, derive an analytical formula for f_T in terms of the extrinsic model parameters of the simplified SSM, which are related to the intrinsic model parameters of a general SSM, and verify its validity for devices with L_g from 260 to 25 nm. In long-channel devices, the effect of the intrinsic output conductance (g_oi) on f_T was negligible. This was because, from the simplified SSM perspective, three model parameters, such as g_{m_ext}, C_{gs_ext} and C_{gd_ext}, were weakly dependent on g_oi. However, in short-channel devices, g_oi was found to play a significant role in degrading f_T as L_g was scaled down. The increase in g_oi in short-channel devices caused a considerable reduction in g_{m_ext} and an overall increase in the total extrinsic gate capacitance, yielding a decrease in f_T with g_oi. Finally, the results were used to infer how f_T is influenced by g_oi in HEMTs, emphasizing that improving electrostatic integrity is also critical importance to benefit fully from scaling down L_g.

• Advances in nano research
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• v.17 no.2
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• pp.137-147
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• 2024

Graphene nanoribbons (GNRs) are considered a promising alternative to graphene for future nanoelectronic applications. However, GNRs-based device modeling is still at an early stage. This research models the electronic properties of n-doped rough-edged 13-armchair graphene nanoribbons (13-AGNRs) and quantum transport properties of n-doped rough-edged 13-armchair graphene nanoribbon field-effect transistors (13-AGNRFETs) at different doping concentrations. Step-up and edge doping are used to incorporate doping within the nanostructure. The numerical real-space nearest-neighbour tight-binding (NNTB) method constructs the Hamiltonian operator matrix, which computes electronic properties, including the sub-band structure and bandgap. Quantum transport properties are subsequently computed using the self-consistent solution of the two-dimensional Poisson and Schrödinger equations within the non-equilibrium Green's function method. The finite difference method solves the Poisson equation, while the successive over-relaxation method speeds up the convergence process. Performance metrics of the device are then computed. The results show that highly doped, rough-edged 13-AGNRs exhibit a lower bandgap. Moreover, n-doped rough-edged 13-AGNRFETs with a channel of higher doping concentration have better gate control and are less affected by leakage current because they demonstrate a higher current ratio and lower off-current. Furthermore, highly n-doped rough-edged 13-AGNRFETs have better channel control and are less affected by the short channel effect due to the lower value of subthreshold swing and drain-induced barrier lowering. The inclusion of dopants enhances the on-current by introducing more charge carriers in the highly n-doped, rough-edged channel. This research highlights the importance of optimizing doping concentrations for enhancing GNRFET-based device performance, making them viable for applications in nanoelectronics.