• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.510-513
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• 2003

Our Zn diffusion into n-type $GaAs_{0.40}P_{0.60}$ used ampoule-tube method to increase IV. N-type epitaxial wafers were preferred by $H_2SO_4$-based pre-treatment. $SiO_2$ thin film was deposited by PECVD for some wafers. Diffusion times and diffusion temperatures respectability are 1, 2, 3 hr and 775, $805^{\circ}C$. LED chips were fabricated by the diffused wafers at Fab. The peak wavelength of all chips showed about $625{\sim}650\;nm$ and red color. The highest IV is about 270 mcd at the diffusion condition of $775^{\circ}C$, 3h for the wafers which didn't deposit $SiO_2$ thin films. Also, the longer diffusion time is the higher IV for the wafers which deposit $SiO_2$ thin films.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.110-114
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• 1990

Double Injection Switching Devices consist of $P^+$ and $n^+$ contact separated by a near intrinsic Semiconductor region containing deep trap. A V-Groove Double Injection Switching Devices were proposed for high voltage performance and Optical gating scheme. The experimental result to demonstrate the feasibility of these devices (Planar type, V-Groove type, Injection Gate mode, Optical Gate mode) for practical application are described.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.114-114
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• 2011

We report a high-performance and air-stable flexible and invisible semiconductor which can be substitute for the n-type organic semiconductors. N-type organic-inorganic nanohybrid superlattices were developed for active semiconducting channel layers of thin film transistors at low temperature of $150^{\circ}C$ by using molecular layer deposition with atomic layer deposition. In these nanohybrid superlattices, self-assembled organic layers (SAOLs) offer structural flexibility, whereas ZnO inorganic layers provide the potential for semiconducting properties, and thermal and mechanical stability. The prepared SAOLs-ZnO nanohybrid thin films exhibited good flexibility, transparent in the visible range, and excellent field effect mobility (> 7cm2/$V{\cdot}s$) under low voltage operation (from -1 to 3V). The nanohybrid semiconductor is also compatible with pentacene in p-n junction diodes.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.964-969
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• 2014

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• Advances in nano research
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• v.2 no.1
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• pp.1-14
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• 2014

Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.237-237
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• 2004

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.21-24
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• 2017

Usually, the oxygen vacancy is an important factor in an oxide semiconductor device because the conductivity is related to the oxygen vacancy, which is formed at the interface between oxide semiconductors and electrodes with an annealing processes. ZTO is made by mixing n-type ZnO and p-type $SnO_2$. Zink tin oxide (ZTO), zink oxide (ZnO) and tin oxide ($SnO_2$) thin films deposited by RF magnetron sputtering and annealed, to generate the oxygen vacancy, were analyzed by XPS spectra. The contents of oxygen vacancy were the highest in ZTO annealed at $150^{\circ}C$, ZnO annealed at $200^{\circ}C$ and $SnO_2$ annealed at $100^{\circ}C$. The current was also increased with increasing the oxygen vacancy ions. The highest content of ZTO oxygen vacancies was obtained when annealed at 150. This is the middle level in compared with those of ZnO annealed at $200^{\circ}C$ and $SnO_2$ annealed at $100^{\circ}C$. The electrical properties of ZTO followed those of $SnO_2$, which acts a an enhancer in the oxide semiconductor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.662-667
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• 2013

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on $p^+/n^+$ source and drain region. However these types of wiggling profile is only observed at the $n^+$ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on next-generation DRAM products.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.328-331
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• 1988

Sealed Interface Local Oxidation (SILO) technology has been investigated using a nitride/oxide/nitride three-layered sandwich structure. P-type silicon substrate was either nitrided by rapid thermal processing, or silicon nitride was deposited by LPCVD method. A three-layered sandwich structure was patterned either by reactive ion etch (RIE) mode or by plasma mode. Sacrificial oxidation conditions were also varied. Physical characterization such as cross-section analysis of field oxide, and electrical characterization such as gate oxide integrity, junction leakage and transistor behavior were carried out. It was found that bird's beak was nearly zero or below 0.1um, and the junction leakages in plasma mode were low compared to devices of the same geometry patterned in RIE mode, and gate oxide integrity and transistor behavior were comparable. Conclusively, SILO process is compatible with conventional local oxidation process.