• Journal of Power Electronics
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• v.5 no.4
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.274-281
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• 2005

A new resonant pulse converter for energy harvesting is proposed. The converter transfers energy from a low-voltage AC current to a battery. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge rectifier having four N-type MOSFETs and a boost converter haying N-type MOSFET and P-type MOSFET instead of diode. Switching of MOSFETs utilizes the capability of the $3^{rd}$ regional operation. The operational principles and switching method for the power control of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs. Simulation and experiment are performed to prove the analysis of the converter operation and to show the possibility of the $\mu$W energy harvesting.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.77-85
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• 1999

By assuming a linearly graded depletion edge approximation in the intrinsic MOS region and by taking into account the mobility variation dependent on both lateral and vertical fields, a physics-based analytical model for a short-channel(n-channel) MOSFET is suggested. Derived expressions for the threshold voltage and the drain current of typical MOSFET is structures could be used in a unified manner for all operating range. The threshold voltage was calculated by changing following variables : channel length, drain-source voltage, source-substrate voltage, p-substrate doping level, and oxide thickness. It is shown that the threshold voltage decreases almost exponentially as the channel length decreases. In addition, the short-channel threshold voltage roll-off, the channel length modulation and the electron mobility degradation can be derived within a satisfactory accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.876-879
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• 2012

In this paper we studied the radiation detection technology which described the radiation level distribution in high radiation area with remotely and safely. The designed radiation mapping system was composed of radiation nodes and radiation station. The radiation nodes could sense the radiation dose values with pMOSFET radiation sensors and transmit them to the radiation station. At the radiation station the received radiation values were merged with a geometric information and visualized at the virtual graphic location. For the functional verification of the above system, we attached the radiation nodes to each corner in our laboratory, executed the mapping tests, and confirmed the designed functions finally.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.1-6
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• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.758-765
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• 1986

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

• Transactions on Electrical and Electronic Materials
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• v.6 no.1
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.242-242
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• 2010

SiO2박막을 이온 감지막으로 이용한 pH농도센서를 제작하였다. 현재 많은 연구중인 pH센서, pH-ISFET(pH-Ion Sensitive Field Effect Transistor)는 용액과 기준전극간의 전기화학적 변위차를 이용하여 pH를 센싱한다. pH-ISFET는 기존 CMOS공정을 그대로 이용할 수 있고, 이온감지막의 변화만으로 다양한 센서를 제작할 수 있어 최근 많은 연구가 진행 중이다. 하지만 FET를 제작하기 위한 공정의 복잡성과 용액의 전위를 정해주고 FET에 바이어스를 인가해줄 기준전극이 반드시 필요하다는 제한성이 있다. 따라서 본 연구에서는 SOI 기판을 이용하여 간단한 구조의 pH센서를 제작하였다. 센서는 (100)결정면을 가지는 p-타입 SOI(Silicon On Insulator)기판을 사용하였으며 포토리소그래피 공정을 이용하여 back-gated MOSFET구조로 제작하였다. 이온감지막으로 사용할 SiO2박막은 RF 스퍼터링을 이용하여 $100{\AA}$ 증착하였다. 바이어스는 기존 pH-ISFET와는 다르게 기준전극 대신 기판을 backgate로 사용하여 FET에 바이어스를 인가해 주었다. pH 용액 주입을 위해 PDMS재질의 챔버를 제작하고 실리콘글루를 이용하여 센서에 부착하였다. pH12부터 pH4까지 단계적으로 누적시키며 챔버에 주입하였고, pH에 따른 드레인전류의 변화를 관찰하였다. pH용액을 챔버에 주입시, pH농도에 따라 제작된 센서의 문턱전압이 오른쪽으로 이동하는 결과를 관찰할 수 있었다. 결과적으로, 구조가 간단한 pseudo MOSFET을 이용하여 pH센서의 적용가능성을 확인하였으며 SiO2박막 역시 본 pH센서의 이온감지막의 역할과 센서의 안정성을 향상시킬 수 있다는 점을 확인하였다.