• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.32-36
• /
• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• Electrical & Electronic Materials
• /
• v.8 no.5
• /
• pp.601-605
• /
• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.3
• /
• pp.401-417
• /
• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.33 no.6
• /
• pp.203-211
• /
• 1984

MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

• Journal of Animal Science and Technology
• /
• v.49 no.4
• /
• pp.481-490
• /
• 2007

An experiment was conducted to investigate the effects of dietary supplementation of MOS, lectin and organic acid mixture(Organic acid F, Organic acid G) on the egg production, egg quality, profile of leukocytes and erythrocytes, small intestinal microflora and immune response in laying hens. A total of 900 Hy-line BrownⓇ laying hens of 48 wks old were assigned to one of the following 6 dietary treatments:control(C), C+AvillamycinⓇ 6ppm, C+MOS 250ppm, C+lectin 12.5ppm, C+Organic acid F(formic acid 35.4%, formate 34.6%, potassium 30.0%) 0.3% and C+0rgarnic acid G(fumaric acid 23%, calcium formate 14%, potassium sorbate 5%, calcium propionate 7%) 0.06%. Each treatment was replicated five times with thirty birds per replicate, housed in 2 bird cages. Feeding trial lasted for 6 wks under 16 hours lighting regimen. All supplemental groups were higher than the control in 6 wks hen-day and hen-housed egg production showing the highest with MOS treatment(P<0.05). Soft & broken egg productions were lower in supplemental groups than in the control except lectin treatment(P<0.05). Eggyolk color of supplemental groups was higher than that of the control except Organic acid G treatment(P<0.05). The values of RBC, HB, MCHC were highest in lectin treatment and lowest in MOS treatment(P<0.05). The numbers of intestinal microflora were not significantly different among the treatments. Serum IgG levels of all supplemental groups were higher than those of the control(P<0.05). In conclusion, for supplementation of antibiotics, immune modulators and organic acid mixture improved production parameters in general. Among the supplements, MOS showed the best performance in egg production and eggyolk color.

• Asian-Australasian Journal of Animal Sciences
• /
• v.28 no.11
• /
• pp.1599-1605
• /
• 2015

Twenty Holstein calves were used to investigate the effects of mannanoligosaccharides (MOS) supplementation in the whole milk on growth performance, faecal score, faecal pH, selected faecal bacterial populations and health during the preweaning period. Healthy calves selected by clinical examination were allocated to one of the two groups (control [CG] and experimental [EG]) at 5 days old. Each group consisted of 5 male and 5 female calves. Each calf in EG was supplemented with 7 g/d of a MOS product (Celmanax) from 5 days to 56 days of age. MOS supplement was mixed with the whole milk once in the morning and administered to the calves in EG via nipple bottle, whereas the calves in CG were fed the whole milk without MOS. Calves were weaned at 56 days of age. The final body weight, average daily weight gain (ADG) and average daily feed intake (ADFI) were statistically similar (p>0.05) but were higher by 3.70%, 6.66%, and 10.97%, respectively, in MOS than in control calves. Feed efficiency (ADG/ADFI) was also similar in two calves group. While faecal scores did not differ on day 5, 7, 14, 21, 28, 42, 49, and 56 between groups, EG had a higher faecal score (p = 0.05) than CG on day 35. Faecal concentration of Lactobacillus was lower (p<0.05) in EG compared with CG. No differences (p>0.05) in faecal concentrations of Bifidobacterium, Clostridium perfringens, and Escherichia coli were found between groups. Although there were no significant differences (p>0.05) in the incidence of diarrhoea, treatment days for diarrhoea and the costs associated with diarrhoea treatments between groups, collectively, the observed reductions in treatment days and the cost of diarrhoea treatments accompanying increases in final body weight, ADG and ADFI for EG may indicate potential benefit of MOS in treatment of diarrhoea.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.43-51
• /
• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.207-210
• /
• 1996

This paper describes the analysis of the operation of the switched snubber in order to depress the surge voltage in the MOS-FET inverter. In this paper, the N-channel MOS-FET which operates faster than the P-channel MOS-FET was used for the inverter circuit. So, the inverter and switched snubber can operate at high-frequency in the order of MHz. The cause of generating the surge voltage in the high frequency inverter has been cleared, and then how to depress the surge voltage using the switched snubber consisting of an N-channel MOS-FET has been given. Furthermore, described is the power loss within the switched snubber which is made of an N-channel MOS-FET. The inverter having the N-channel MOS-FET used as a switched snubber can drive such a low impedance load such as mega-sonic transducer for a mega-sonic studied cleaner sufficiently.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.4
• /
• pp.373-377
• /
• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.6
• /
• pp.28-36
• /
• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.