• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.32-36
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.601-605
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• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• 한국통신학회논문지
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• 제19권3호
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• pp.401-417
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• 1994

본 논문에서는 논리 모니터링 방식에 의해 stuck-at(s-at)고장, stuck-open(s-op)고장 및 stuck on(s-on) 고장을 검출하기 위한 Domino CMOS회로의 테스트용이화 셀계기법을 제안한다. Domino CMOS게이트내 nMOS트랜지스터들의 s-op고장과 s-on고장을 검출하기 위하여 한개의 pMOS 트랜지스터를 부가하고 단일 게이트 및 다단 Domino CMOS회로내 인버어터의 pMOS트랜지스터 s-on 고장을 검출하기 위해서 한개의 nMOS트랜지스터를 부가한가. 부가된 트랜지스터는 Domino CMOS를 테스트 모드에서 pseudo nMOS회로로 동작하도록 만든다. 따라서 일반 domino CMOS회로의 테스트 시 회로지연에 의한 오동작을 방지하는 선충전(precharge phase)과 논리결정(evaluation phase)의 이상(two-phase)동작을 필요로 하지 않아 테스트 시간과 테스트 생성의 복잡도를 줄일 수 있게 된다. 제안된 회로에서는 대부분의 고장들이 단일 테스트 패턴에 의해 검출되는데 이에따라 경로지연이나 타임스큐, 전하재분배 및 그리치 등에 의해 테스트가 무효화되는 것을 피할 수 있으며 테스트 패턴 생성을 위하여 기존의 자동 테스트패턴생성기(ATPG)를 이용할 수 있는 장점을 갖는다.

• 대한전기학회논문지
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• 제33권6호
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• pp.203-211
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• 1984

MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

• Journal of Animal Science and Technology
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• 제49권4호
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• pp.481-490
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• 2007

본 시험은 대조구, 항생제 처리구:Avilla- mycin?? 6ppm, MOS 처리구:MOS 250ppm, lectin 처리구:Mannosespepecific lectin 12.5ppm, Organic acid F 처리구:FORMI??(formic acid 35.4%, formate 34.6%, potassium 30.0%) 0.3%, Organic acid G처리구: GALLACID?? 0.06% 등 6처리구를 두고 이들 처리가 산란계에 미치는 영향을 비교 평가하기 위하여 생산성, 혈액성상, 혈청 IgG, 장내 미생물 균총을 조사하였다. 사양시험은 48주령의 산란계(Hy-Line Brown??) 900수를 선별하여 6처리, 5반복, 반복당 15케이지, 케이지당 2수씩 A형 2단 케이지에 수용하고 randomized block design으로 배치하였다. 6주 동안의 산란율(hen-day, hen- house egg production)에서는 MOS 처리구가 가장 높은 산란율을 보였고 모든 첨가구가 대조구보다 산란율이 높았다(P<0.05). 난중은 lectin 처리구가 가장 높았으며 모든 첨가구들이 대조구보다 높은 경향이 있었다. 연파란율은 lectin 처리구를 제외한 모든 첨가구들이 대조구보다 낮았다(P<0.05). 난황색은 Organic acid G 처리구를 제외한 모든 첨가구들이 대조구보다 높았다(P<0.05). Haugh unit는 lectin 처리구가 가장 높았으며 모든 첨가구들이 대조구보다 높았다. Leukocytes 중 SI는 lectin 처리구가 가장 높았다(P<0.05). Erythrocytes 중 RBC, HB, MCHC는 lectin 처리구가 가장 높았으며 MOS 처리구가 가장 낮았다(P<0.05). 장내 미생물에서는 처리구간에 유의적인 차이는 없었으나 Lactobacilli 수는 대조구보다 첨가구들이 높은 경향이 있었고 Cl. perfringens 수는 Organic acid F를 제외한 모든 첨가구들이 대조구보다 낮은 경향이 있었다. 혈청 IgG 농도는 MOS 처리구가 가장 높았으며 모든 첨가구들이 대조구보다 유의적으로 높았다(P<0.05). 결론적으로 본 시험에서 사용된 면역조절제(MOS, Lectin)와 유기산제는 산란계에서 항생제(Avilamycin??)와 유사한 생산성을 나타내어 항생제 대체제로서 산란계의 생산성을 효과적으로 개선 할 수 있으며 특히 이중에서 MOS의 생산성 개선효과가 가장 높았다.

• Asian-Australasian Journal of Animal Sciences
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• 제28권11호
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• pp.1599-1605
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• 2015

Twenty Holstein calves were used to investigate the effects of mannanoligosaccharides (MOS) supplementation in the whole milk on growth performance, faecal score, faecal pH, selected faecal bacterial populations and health during the preweaning period. Healthy calves selected by clinical examination were allocated to one of the two groups (control [CG] and experimental [EG]) at 5 days old. Each group consisted of 5 male and 5 female calves. Each calf in EG was supplemented with 7 g/d of a MOS product (Celmanax) from 5 days to 56 days of age. MOS supplement was mixed with the whole milk once in the morning and administered to the calves in EG via nipple bottle, whereas the calves in CG were fed the whole milk without MOS. Calves were weaned at 56 days of age. The final body weight, average daily weight gain (ADG) and average daily feed intake (ADFI) were statistically similar (p>0.05) but were higher by 3.70%, 6.66%, and 10.97%, respectively, in MOS than in control calves. Feed efficiency (ADG/ADFI) was also similar in two calves group. While faecal scores did not differ on day 5, 7, 14, 21, 28, 42, 49, and 56 between groups, EG had a higher faecal score (p = 0.05) than CG on day 35. Faecal concentration of Lactobacillus was lower (p<0.05) in EG compared with CG. No differences (p>0.05) in faecal concentrations of Bifidobacterium, Clostridium perfringens, and Escherichia coli were found between groups. Although there were no significant differences (p>0.05) in the incidence of diarrhoea, treatment days for diarrhoea and the costs associated with diarrhoea treatments between groups, collectively, the observed reductions in treatment days and the cost of diarrhoea treatments accompanying increases in final body weight, ADG and ADFI for EG may indicate potential benefit of MOS in treatment of diarrhoea.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.207-210
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• 1996

This paper describes the analysis of the operation of the switched snubber in order to depress the surge voltage in the MOS-FET inverter. In this paper, the N-channel MOS-FET which operates faster than the P-channel MOS-FET was used for the inverter circuit. So, the inverter and switched snubber can operate at high-frequency in the order of MHz. The cause of generating the surge voltage in the high frequency inverter has been cleared, and then how to depress the surge voltage using the switched snubber consisting of an N-channel MOS-FET has been given. Furthermore, described is the power loss within the switched snubber which is made of an N-channel MOS-FET. The inverter having the N-channel MOS-FET used as a switched snubber can drive such a low impedance load such as mega-sonic transducer for a mega-sonic studied cleaner sufficiently.

• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• 전자공학회논문지D
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• 제35D권6호
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• pp.28-36
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• 1998

낮은 전압에서 고속으로 동작이 가능한 고속 비반전 SOI 버퍼 회로를 제안하였다. 제안된 버퍼 회로는 효율적으로 연결된 보조 MOS 트랜지스터를 경유하여 바디 전압이 동적으로 제어된다. 소자 시뮬레이션을 수행하여 바디가 보조 MOS 트랜지스터로 제어되는 MOS 소자의 전류 구동능력을 보이고 기존의 다른 방식과 비교하였다. SPICE를 이용한 회로 시뮬레이션을 통하여 제안된 버퍼 회로의 지연시간 특성을 조사하고 같은 사양을 가진 기존의 SOI CMOS 버퍼 회로와 비교하였다. 같은 면적을 기준으로 하여 제안된 버퍼회로는 기존의 버퍼 회로에 비해 1.2 V의 동작전압과 2 pF의 부하용량에 대하여 약 36% 지연 시간 단축을 보였다.