• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.505-508
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• 2024

금융산업의 디지털 전환은 사용자에게 편리함을 제공하지만 기존에 존재하지 않던 보안상 취약점을 유발했다. 이러한 문제를 해결하기 위해 기계학습 기술을 적용한 사기 거래 탐지 시스템에 대한 연구가 활발하게 이루어지고 있다. 하지만 모델 학습 과정에서 발생하는 데이터 불균형 문제로 인해 오랜 시간이 소요되고 탐지 성능이 저하되는 문제가 있다. 본 논문에서는 실시간 데이터 오버 샘플링을 통해 이상 거래 탐지 시 데이터 불균형 문제를 해결하고 모델 학습 시간을 개선한 새로운 이상 거래 탐지 시스템(Fraud Detection System, FDS)을 제안한다. 본 논문에서 제안하는 SMOTE(Synthetic Minority Oversampling Technique)를 적용한 LSTM(Long-Short Term Memory) 알고리즘 기반의 FDS 프레임워크는 종래의 LSTM 알고리즘 기반의 FDS 모델과 비교했을 때, 데이터 사이즈가 96.5% 감소했으며, 정밀도, 재현율, F1-Score 가 34.81%, 11.14%, 22.51% 개선되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.823-832
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• 2011

In this paper, an efficient blind carrier frequency offset (CFO) estimation method in orthogonal frequency division multiplexing (OFDM) systems is proposed. In the proposed method, we obtain two time different received OFDM symbols by using both the cyclic prefix and oversampling technique, and a cost function is defined by using the two OFDM symbols. We show that the cost function can be approximately expressed as a cosine function. Using a property of the cosine function, a formular for estimating the CFO is derived. The estimator of the CFO requires three independent cost function values calculated at three different points of frequency offset. The proposed method is very efficient in computational complexity since no searching operation for the minimum cost value is required. The proposed method reduces 97% of the amount of FFT computation, compared with the ML method. Unlike the conventional methods such as the ML method and the MUSIC] method, the accuracy of the proposed method is independent of the searching resolution since the closed form solution exists. The computer simulation shows that the performance of the proposed method is superior to those of the MUSIC and the ML method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.8
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• pp.1226-1237
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• 1993

For data transmission over strictly band-limited non-ideal channels, different types of filters with arbitrary responses are needed. In this paper. we proposed two efficient techniques for the design of such FIR filters whose response is specified in either the time or the frequency domain. In particular when a fractionally-spaced structure is used for the transceiver, these filters can be efficiently designed by making use of characteristics of oversampling. By using a minimum mean-squared error criterion, we design a fractionally-spaced FIR filter whose frequency response can be controlled without affecting the output error. With proper specification of the shape of the additive noise signals, for example, the design results in a receiver filter that can perform compromise equalization as well as phase splitting filtering for QAM demodulation. The second method ad-dresses the design of an FIR filter whose desired response can be arbitrarily specified in the frequency domain. For optimum design, we use an iterative optimization technique based on a weighted least mean square algorithm. A new adaptation algorithm for updating the weighting function is proposed for fast and stable convergence. It is shown that these two independent methods can be efficiently combined together for more complex applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the Korean Data and Information Science Society
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• v.24 no.3
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• pp.411-425
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• 2013

The importance and necessity of the credit loan are increasing over time. Also, it is a natural consequence that the increase of the risk for borrower increases the risk of non-performing loan. Thus, we need to predict accurately in order to prevent the loss of a credit loan company. Our final goal is to build reliable and accurate prediction model, so we proceed the following steps: At first, we can get an appropriate sample by using several resampling methods. Second, we can consider variety models and tools to fit our resampling data. Finally, in order to find the best model for our real data, various models were compared and assessed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.2
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• pp.56-63
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• 2003

We investigate some implementation factors that affect the performance of multi-rate parallel interference cancellers (PICs) for the international mobile telecommunications-2000 (IMT-2000) 3rd-generation partnership project (3GPP) system. We consider the simple multi-rate PIC [1,2] that can remove effectively multiple access interference (MAI) through block-based detection and sample-based cancellation in asynchronous user environments. The PIC structure has significantly lower complexity as compared with that of the existing scheme, especially as the number of users increases. We analyze the effects of timing error, oversampling rate, unsynchronized users and/or outer-cell interference, and the number of Quantization bits on the PIE performance through extensive computer simulations. The models for such factors and the optimum parameters are drawn. Finally, we evaluate the receiver complexities of the PIC receivers employing using the advanced removal scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.