• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.74-77
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• 2002

Ferroelectric Random Access Memory(FRAM) and MEMS applications require noble metal or refractory metal oxide electrodes. In this study, Ru thin films were etched using $O_2$+10% $CF_4$ plasma in an inductively coupled plasma(ICP) etching system. The etch rate of Ru thin films was examined as function of rf power, DC bias applied to the substrate. The enhanced etch rate can be obtained not only with increasing rf power and DC bias voltage, but also with small addition $CF_4$ gas. The selectivity of $SiO_2$ over Ru are 1.3. Radical densities of oxygen and fluorine in $CF_4/O_2$ plasma have been investigated by optical emission spectroscopy(OES). The etching profiles of Ru films with an photoresist pattern were measured by a field emission scanning electron microscope (FE-SEM). The additive gas increases the concentration of oxygen radicals, therefore increases the etch rate of the Ru thin films and enhances the etch slope. In $O_2$+10% $CF_4$ plasma, the etch rate of Ru thin films increases up to 10% $CF_4$ but decreases with increasing $CF_4$ mixing ratio.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.846-851
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• 2007

In this work, the etching characteristics of $Ge_2Sb_2Te_5(GST)$ thin films were investigated using an inductively coupled plasma (ICP) of $Cl_2/Ar$ gas mixture. To analyze the etching mechanism, an optical emission spectroscopy (OES) and surface analysis using X-ray photoelectron spectroscopy (XPS) were carried out. The etch rate of the GST films decreased with decreasing Ar fraction. At the same time, high selective etch rate over $SiO_2$ films was obtained and the selectivity over photoresist films decreased with increasing the he fraction. From XPS results, we found that Te halides were formed at the etching surface and Te halides limited the etch rate of the GST films.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.9
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• pp.438-443
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• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Journal of the Korean Ceramic Society
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• v.36 no.9
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• pp.946-953
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• 1999

The etching characteristics of Er-doped sodium borosilicate glass film for the planar optical waveguides were investigated using reactive ion etching. The etch rate decreased as the pressure in creased but increased as the RF power increased. The etch rate increased as the flow rate C2F gas and the amount of O2 addition increased but decreased over critical point (C2F6 7,5 accm O2 20%) The etch rate was 180${\AA}$/min under C2F6 7.5 sccm O2 20% RF power 270 W, pressure 150 mTorr. With this optimum etching condition and subsequent heat treatment at 975$^{\circ}C$ for 30 minutes planar optical waveguides having improved sidewall roughness were fabricated successfully.

• ETRI Journal
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• v.24 no.5
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• pp.398-400
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• 2002

Using $Cr_2O_3$ thin film, we developed a novel etch-stop technique for the protection of silicon surface morphology during deep ion coupled plasma etching of silica layers. With this technique we were able to etch a silica trench with a depth of over 20 ${\mu}m$ without any damage to the exposed silicon terrace surface. This technique should be well applicable to fabricating silica planar lightwave circuit platforms for opto-electronic hybrid integration.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.138-140
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• 2006

A new diagnosis model was constructed by combining atomic force microscopy (AFM), wavelet, and neural network. Plasma faults were characterized by filtering AFM-measured etch surface roughness with wavelet. The presented technique was evaluated with the data collected during the etching of silicon oxynitride thin film. A total of 17 etch experiments were conducted. Applying wavelet to AFM, surface roughness was detailed into vertical, horizon%at, and diagonal components. For each component, neural network recognition models were constructed and evaluated. Comparisons revealed that the vertical component-based model yielded about 30% improvement in the recognition accuracy over others. The presented technique was evaluated with the data collected during the etching of silicon oxynitride thin film. A total of 17 etch experiments were conducted

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.501-504
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• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.45-50
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• 2022

The etching with high selectivity of silicon dioxide over silicon nitride is essential in semiconductor fabrication, and gas phase etch (GPE) can increase the competitiveness of the selective dielectric etch. In this work, GPE of plasma enhanced chemical vapor deposited SiO₂ was performed, and the effects of process parameters, such as temperature, partial pressure ratio, and gas supply cycle, are investigated in terms of etch rate and within wafer uniformity. Employing multiple regression analysis, the importance of each parameter elements is analyzed.