• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.11
• /
• pp.2479-2485
• /
• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.5C
• /
• pp.411-421
• /
• 2002

In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.17-22
• /
• 2008

This paper presents a low-power and small-area pulse width modulator by light intensity for photoflash. Light intensity controller is achieved by using capacitor, photodiode, and comparator. The proposed circuit designs digital circuit to reduce static power consumption except comparator. And IGBT driver has short circuit protection using delay cell. The pulse width modulator has the operating range of $V_{MS}$ from 0.5V to 2.5V and pulse width of output from 0.14ms to 1.65ms at 300Hz. The pulse width modulator fabricated in $0.35-{\mu}m$ CMOS technology occupies $0.85mm{\times}0.56mm$. This circuit consumes 3.0mW at 300Hz and 3.0V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.7
• /
• pp.762-768
• /
• 2003

This paper reports the effects of gain flatness for linearity improvement of feedforward power amplifier fur IMT-2000 band. To investigate the operational characteristics for gain flatness of each amplifier, WCDMA 4FA input signal was used and measured 10 W output power. Especially, linearity improvement for variation of gain flatness of each amplifier was investigated that have an effect on linearity improvement such as delay line, phase, and amplitude imbalances. Variation of gain flatness of main amplifier is 40 MHz and of error amplifier is 40 MHz and 80 MHz bandwidth, respectively. Measured results, gain flatness of main amplifier is less than 1.5 dB and of error amplifier is less than 0.5 dB for more than 20 dB improvement at 5 MHz offset. In addition to that results, the characteristics of feedforward amplifier are drastically varied by gain flatness of error amplifier and it is shown that gain flatness of error amplifier is more important factor for linearity improvement.

• Journal of Sensor Science and Technology
• /
• v.27 no.4
• /
• pp.254-258
• /
• 2018

A Wi-Fi signal network (WSN) system is introduced in this paper. This system consists of several data-transmitting sensor modules and a data-receiving server. Each sensor module and the server contain a unique intranet IP address. A piezoelectric accelerometer with a bandwidth of 12 kHz, a 24-bit analog-digital converter with a sampling rate of 15.625 kS/s, a 32-bit microprocessor unit, and a 1-Mbps Wi-Fi module are used in the data-transmitting sensor module. A 300-Mbps router and a PC are used in the server. The system is verified using an accelerometer calibrator. The voltage output from the sensor is converted into 24-bit digital data and transmitted via the Wi-Fi module. These data are received by a Wi-Fi router connected to a PC. The input frequencies of the accelerometer calibrator (320 Hz, 640 Hz, and 1280 Hz) are used in the data transfer verification. The received data are compared to the data retrieved directly from the analog-to-digital converter used in the sensor module. The comparison shows that the developed system represents the original data considerably well. Theoretically, the system can acquire vibration signals from 600 sensor modules at an accelerometer bandwidth of 15.625 kHz. However, delay exists owing to software processes, multiplexing between sensor modules, and the use of non-real time operating system. Hence, it is recommended that this system may be used to acquire vibration signals with up to 10 kHz, which is approximately 70% of the theoretical maximum speed of the system. The system can be upgraded using parts with higher performance

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.87-94
• /
• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.39-46
• /
• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.34-43
• /
• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.4
• /
• pp.430-435
• /
• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.1
• /
• pp.301-306
• /
• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.