• Journal of Navigation and Port Research
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• v.44 no.2
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• pp.119-127
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• 2020

In this study, the current state of management efficiency of ocean carriers in Korea and the factors affecting them were analyzed. The purpose of this research is to enhance global competitiveness of ocean carriers by presenting suggestions that can improve management efficiency based on the analysis results. The measurement of management efficiency was made using the DEA model. The results of testing the adequacy of the input and output variables used are as follows. Appropriate inputs are total assets, cost of goods sold, charter expenses, sales and general management expenses, and interest expenses. Appropriate variables are sales, operating income, and operating cash flow. According to the analysis results of the DEA model by these variables, inefficient carriers (78%) are nearly four times more than efficient carriers(22%). However, container carriers have the most improved management efficiency compared to 2016 and 2017. According to the panel regression analysis, the charter rate has the greatest negative impact on efficiency (CRS), and the debt rate has a significant negative impact. Thus, it appears that reducing the charter size and the debt-to-sale rate facilitate improvement of the management efficiency of ocean carriers. Additionally, the pre-sales tax return rate, value added rate, total asset turnover rate, and the scale variable and interest coverage rate have a positive (+) effect. Thus ocean carriers should restore their global competitiveness by improving management efficiency by securing stable cargoes increasing sales profitability from the cost management perspective, increasing productivity, and enhancing the efficiency of their total assets through efficient fleet management.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.673-676
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• 2015

Digital Pre-Distortion (DPD) is a linearization technique for nonlinear power amplifiers (PAs) by implementing inverse function of the PA at baseband digital stage. To obtain proper DPD parameters, a feedback path is required to convert the PA output to a baseband signal, and a memory is also needed to store the feedback signals. DPD parameters are usually found by an adaptive algorithm from the feedback samples. However, for the adaptive algorithm to converge to a reliable solution, long feedback samples are required, which increases convergence time and hardware complexity. In this paper, we propose a DPD technique that requires relatively short feedback samples. From the observation that the convergence time of the adaptive algorithm highly depends on the initial condition, this paper iteratively utilizes the feedback samples while keeping and using the converged DPD parameters at the former iteration as the initial condition at the current iteration. Computer simulation results show that the proposed method performs better than the conventional technique while the former requires much shorter feedback samples than the latter.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.89-95
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• 2009

Tracking the Maximum Power Point(MPP) of a photovoltaic(PV) array is usually an essential part of a PV system. The problem considered by MPPT techniques is to find the voltage $V_{MPP}$ or current $I_{MPP}$ at which a PV array should operate to generate the maximum power output PMPP under a given temperature and irradiance. The MPPT control methods, such as the perturb and observe method and the incremental conductance method require microprocessor or DSP to determine if the duty cycle should be increased or not. This paper proposes a simple and fast analog MPPT method. The proposed control scheme will track the MPP very fast and its hardware implementation is so simple, compared with the conventional techniques. The new algorithm has successfully tracked the MPP, even in case of rapidly changing atmospheric conditions, and Has higher efficiency than ordinary algorithms.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.2
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• pp.63-68
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• 2005

Total 12 units of high power klystron-modulator systems as microwave source are under operation for 2.5 GeV electron linear accelerator in Pohang Light Source (PLS) linac. The klystron-modulator system has an important role for the stable operation to improve an availability statistics of overall system performance of klystron-modulator system. RF power and beam power of klystron are precisely measured for the effective control of electron beam. A precise measurement and measurement equipment with good response characteristics are demanded for this. Input power of klystron is calculated from the applied voltage and the current on its cathode. Tiny measurement error severely effects RF output power value of klystron. Therefore, special care is needed to measure precise beam voltage. Capacitive voltage divider (CVD), which divides input voltage as capacitance ratio, is intended for the measurement of a beam voltage of 400 kV generated from the klystron-modulator system. Main parameter to determine standard capacitance in the high arm of CVD is dielectric constant of insulation oil. Therefore CVD should be designed to have a minimum capacitance variation due to voltage, frequency and temperature in the measurement range. This paper will be present and discuss the design concept and analysis of capacitive voltage divider for a pulsed high-voltage measurement, and the empirical relations between capacitance effects and oil temperature variation.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2004.11a
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• pp.543-547
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• 2004

Visualization of construction process simulation and physical modeling were considered to overcome the limitations of current graphical simulation. The output of discrete-event simulation programs which are the most common mathematical statistical simulation tool for construction processes were analyzed for the visualization of earthmoving process that dealing with objects without fixed. Object-oriented models for equipment, material and work environments were devised to effectively visualize the numerical simulation results of the working time, the queuing time as well as the amount resources etc. The oscillation of the crane's cable and the lifted material that should be considered to rationally modeled and simulated by construction graphical simulation. The derived equation of motion was solved by numerical analysis procedure. Then obtained results was used for physical modeling.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.6
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• pp.307-315
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• 2003

This paper proposes a novel simulation method of WPGS (Wind Power Generation System). The rotation speed control method of turbine under variable wind speed using the pitch control is proposed. Moreover, when wind speed exceeds the cut-out wind speed, the turbine will be stopped by controlling pitch angle to 90$^{\circ}$, otherwise it will be controlled to steady-state operation. For the purpose of effective simulation, the SWRW (Simulation method for WPGS using Real Weather condition) is used for the utility interactive WPGS simulation in this paper, in which those of three topics for the WPGS simulation: user-friendly method, applicability to grid-connection and the utilization of the real weather conditions, are satisfied. It is impossible to consider the real weather conditions in the WPGS simulation using the EMTP type of simulators and PSPICE, etc. External parameter of the real weather conditions is necessary to ensure the simulation accuracy. The simulation of the WPGS using the real weather conditions including components modeling of wind turbine system is achieved by introducing the interface method of a non-linear external parameter and FORTRAN using PSCAD/EMTDC in this paper. The simulation of long-term, short-term, over cut-out and under cut-out wind speeds will be peformed by the proposed simulation method effectively. The efficiency of wind power generator, power converter and flow of energy are analyzed by wind speed of the long-term simulation. The generator output and current supplied into utility can be obtained by the short-term simulation. Finally, transient-state of the WPGS can be analyzed by the simulation results of over cut-out and under cut-out wind speeds, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.128-134
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• 2010

In this paper, a high-power 20-way stripline power divider with low insertion loss and low side lobe level is successfully designed, fabricated and measured as a feed network for an S-band linear array antenna having Dolph-Chebyshev current distribution which has a narrow beam width and very low side lobe level (SLL). The 20-way stripline power divider consists of an 8-way power divider, three 4-way power dividers and three ring hybrids. It utilizes a T-junction structure as a basic element for power dividing. Notches and modified input/output N-to-stripline transitions are used for improving insertion loss and return loss. The fabricated power divider shows insertion loss less than 0.3 ㏈ and rms phase mismatch less than 8o in the full bandwidth. A final 40-way power divider is synthesized by combining symmetrically two 20-way power dividers and is expected to have SLL over 40 dB, based on the measured results of the 20-way power divider.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.61-64
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• 2002

We have optimally designed and implemented by a monolithic microwave integrated circuit(MMIC) the low noise amplifier(LNA) of 5.8GHz band composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication using a depletion-mode GaAs MESFET. The LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18㎃, The gain at center frequency 5.8GHz is 13.4dB, Noise figure(NF) is 1.94dB, Input 3rd order intercept point(lIPS) is 3dBm, and Input return loss(5$_{11}$) and Output return loss(S$_{22}$) is -l8dB and -13.3dB, respectively. The circuit size is 1.2$\times$O.7$\textrm{mm}^2$.EX>.>.