• 전기학회논문지P
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• 제56권2호
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• pp.83-89
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• 2007

The LC filter design procedure of the inverter output filter is described. The transfer function of the filter output voltage to the load current is described with the capacitor value and the system time constant considering the system controller. By using the closed form of the relation between the filter capacitor value and the system time constant, the capacitor value can be calculated with the given system time constant and vice versa. It is more practical for the implementation of power and control circuit of inverter. And as the effect of the load current to the voltage distortion can be calculated from the closed form, it is possible to analyze the system how much the voltage waveform is distorted in case of the nonlinear load. All the proposed design procedure is verified with the simulation and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 전문대학교육위원
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• pp.206-211
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• 2005

The LC filter design procedure of the inverter output filter is described. The transfer function of the filter output voltage to the load current is described with the capacitor value and the system time constant considering the system controller. By using the closed form of the relation between the filter capacitor value and the system time constant, the capacitor value can be calculated with the given system time constant and vice versa. It is more practical for the implementation of power and control circuit of inverter. And as the effect of the load current to the voltage distortion can be calculated from the closed form, it is possible to analyze the system how much the voltage waveform is distorted in case of the nonlinear load. All the proposed design procedure is verified with the simulation and experimental results.

• Journal of Power Electronics
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• 제16권2호
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

• Journal of Power Electronics
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• 제13권1호
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• pp.20-30
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• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• 전기학회논문지
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• 제60권6호
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• pp.1152-1162
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• 2011

In this paper, a single-phase DC-AC inverter using two embedded Z-source converters is proposed. The proposed inverter is composed of two embedded Z-source converters with common DC source and output AC load. The output AC voltage of the inverter is obtained by the difference of output capacitor voltages of each converter. The output voltage of each converter take shape of the asymmetrical AC waveform centering zero voltage. Therefore, the proposed inverter can generate the same output voltage despite low VA rating L-C elements, compared to the conventional inverter using high DC voltage with AC ripple. To verify the validity of the proposed system, the PSIM simulation was achieved under the condition of rapid increase of DC source (110[V]${\rightarrow}$150[V]) and R-load (50[${\Omega}$]${\rightarrow}$300[${\Omega}$]). For controlling the voltage of the inverter system, the one-cycle controller was adopted. As results, the proposed inverter output the constant AC voltage (220[V]rms/60[Hz]) for all conditions. Also, the R-L load and nonlinear diode load were adopted for the proposed inverter loads, and we could know that the its output voltage characteristics were as good as the pure R-load. Finally, the RMS and THD of output AC voltage were examined for the different loads, input DC voltages and reference voltage signals.

• 조명전기설비학회논문지
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• 제26권5호
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• pp.71-78
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• 2012

This paper presents a digital control solution to process capacitor current feedback of high performance single-phase UPS for non-linear loads. In all UPS the goal is to maintain the desired output voltage waveform and RMS value over all unknown load conditions and transient response. The proposed UPS uses instantaneous load voltage and filter capacitor current feedback, which is based on the double regulation loop such as the outer voltage control loop and inner current control loop. The proposed DSP-based digital-controlled PWM inverter system has fast dynamic response and low total harmonic distortion (THD) for nonlinear load. The control system was implemented on a 32bit Floating-point DSP controller TMS320C32 and tested on a 5[KVA] IGBT based inverter switching at 11[Khz]. The validity of the proposed scheme is investigated through simulation and experimental results.

• Journal of Power Electronics
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• 제5권3호
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• pp.190-197
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• 2005

This paper presents a technique to reduce the low frequency ripple voltage of the dc output in a BIFRED converter with a small-sized energy storage capacitor. The proposed pulse width control method can be effectively used to suppress the low frequency ripple appeared in the dc output and still maintains generally good performance such as low THD of input line current and a high power factor. Using the small-sized energy storage capacitor, it has better merits of low cost and smaller size than a conventional BIFRED converter. The proposed technique is illustrated its validity and effectiveness through simulations.

• Journal of Power Electronics
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• 제13권6호
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• pp.928-938
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• 2013

This paper proposes a novel control method for a multi-output switched-resonant converter. Output voltage can be regulated against variations in the supply voltage and load by controlling the voltage of the resonant capacitor (pulse amplitude control). Precise control is possible when pulse amplitude control is combined with pulse number control. The converter is analyzed, and design considerations are explained by using examples. Control implementation is described and load regulation and ripples are analyzed by simulation and hardware results. The topology is modified to obtain an additional negative output without any additional hardware other than a diode. The analysis of such a triple output converter with two positive outputs and one negative output is conducted and confirmed. The topology and control scheme are scalable to any number of outputs.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2227-2236
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• 2017

In order to solve the neutral-point voltage fluctuation problem of three-phase three-level T-type inverters (TPTLTIs), the unbalance characteristics of capacitor voltages under different switching states and the mechanism of neutral-point voltage fluctuation are revealed. Based on the mathematical model of a TPTLTI, a feed-forward voltage balancing control strategy of DC-link capacitor voltages error is proposed. The strategy generates a DC bias voltage using a capacitor voltage loop with a proportional integral (PI) controller. The proposed strategy can suppress the neutral-point voltage fluctuation effectively and improve the quality of output currents. The correctness of the theoretical analysis is verified through simulations. An experimental prototype of a TPTLTI based on Digital Signal Processor (DSP) is built. The feasibility and effectiveness of the proposed strategy is verified through experiment. The results from simulations and experiment match very well.

• Journal of Power Electronics
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• 제13권5호
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• pp.766-778
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• 2013

The depletion of natural resources and renewable energy sources, such as photovoltaic (PV) energy, has been highlighted for global energy solution. The PV power control unit in the PV power-generation technology requires a high step-up DC-DC converter. The conventional step-up DC-DC converter has low efficiency and limited step-up ratio. To overcome these problems, a novel high step-up DC-DC converter using an isolated switched capacitor cell is proposed. The step-up converter uses the proposed transformer and employs the switched-capacitor cell to enable integration with the boost inductor. The output of the boost converter and isolated switched-capacitor cell are connected in series to obtain high step-up with low turn-on ratio. A hardware prototype with 30 V to 40 V input voltage and 340 V output voltage is implemented to verify the performance of the proposed converter. As an extended version, another novel high step-up isolated switched-capacitor single-ended DC-DC converter integrated with a tapped-inductor (TI) boost converter is proposed. The TI boost converter and isolated-switched-capacitor outputs are connected in series to achieve high step-up. All magnetic components are integrated in a single magnetic core to lower costs. A prototype hardware with 20 V to 40 V input voltage, 340 V output voltage, and 100 W output power is implemented to verify the performance of the proposed converter.