• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.11
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• pp.60-66
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• 2007

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop multiple split ring resonator (OLMSRR) is presented for reducing the phase noise property. The square-shaped multiple split ring resonator (MSRR) having the form of the microstrip square open loop is investigated to realize this property. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator (OLSRR) as well as the conventional microstrip line resonator, the microstrip square OLMSRR has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power suppIy has the phase noise of $-124.5\;{\sim}\;-122.0\;dBc/Hz$ @ 100 kHz in the tuning range, $5.746\;{\sim}\;5.84\;GHz$. The figure of merit (FOM) of this VCO is $-203.96\;{\sim}\;-201.6\;dBc/Hz$ @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using the microstrip square open loop resonator and VCO using microstrip square OLSRR, the phase noise property of VCO using the proposed resonator has been improved in 25.66 dB, 8.34 dB, and 4.5 dB, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1176-1183
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• 2003

In this paper, miniature voltage-controlled oscillator(VCO) for 1.6 ㎓ PCS band is designed and implemented using the LTCC technique. Circuit level design using commercial components is performed, and passive L, C elements embedded in LTCC substrate is optimized by simulation tools. Embedded passive components are modeled into equivalent circuits and their circuit parameters are extracted for circuit simulation. Utilizing the designed embedded passive elements and 21 layers LTCC substrate, VCO with 4.0${\times}$4.0${\times}$1.6 ㎣ dimensions is designed and fabricated. Developed VCO operates in 2.7 V with 8.5 ㎃ current consumption. The phase noise performance of VCO is below -112.61 ㏈c/㎐ at 100 ㎑ offset and harmonic suppression characteristics is measured above -30 ㏈.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.96-99
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• 2001

In this paper, we present the simulation results of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonator, the oscillator and the buffer circuit. using EM simulator and nonlinear RF circuit simulator. EM simulator is used for obtaining the EM(Electromagnetic) characteristics of the conductor pattern as well as designing the multi-layer VCO. Obtained EM characteristics were used as real components in nonlinear RF circuit simulation. Finally the overall VCO was simulated using the nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont 951AT, which will be applied for LTCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 4.5[dBm], the phase noise was -104[dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of 9.5[mA]. The size of VCO is $6{\times}9{\times}2mm$(0.11[cc]).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.492-498
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• 2002

In this paper, we present the simulation results of multi-layer VCO(voltage controlled oscillator), which is composed of resonator, oscillator, and buffer circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for obtaining the EM(Electromagnetic) characteristics of conductor pattern as well as designing the multi-layer VCO. Obtained EM characteristics were used as real components in nonlinear RF circuit simulation. Finally the overall VCO was simulated by the nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was Dupont 951AT, which will be applied for LTCC process. The structure of multi-layer VCO is constructed with 4 conducting layer. Simulated results showed that the output level was about 4.5 [dBm], the phase noise was -104 [dBc/Hz] at 30 [kHz] offset frequency, the harmonics -8 dBc, and the control voltage sensitivity of 30 [MHz/V] with a DC current consumption of 9.5 [mA]. The size of VCO is $6{\times}9{\times}2 mm$(0.11 [cc]).

• Journal of Advanced Navigation Technology
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• v.8 no.1
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• pp.57-65
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• 2004

In this paper, keeping pace with light weight, pocket-size, lower-price, we design VCO(Voltage Controlled Oscillator) X/Ku band for using at public RD(Radar Detector) to apply to controlled voltage on base in transistor which used as a oscillator, without using varactor diode in part of VCO tuner. As a result of simulation, we conclude VCO could be have 110 MHz by controlled voltage 4.25 V to 4.80 V and show its output 9.63 dBm at operating frequency, 11.46 GHz, and its phase noise -107.2 dBc at 1 MHz offset frequency. So it turned out suitable performance for commercial use.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4A
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• pp.214-218
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• 2012

In this paper, we reported on a high performance waveguide VCO(voltage controlled oscillator) for FMCW applications. The waveguide VCO consists of a GaAs Gunn diode, a varactor diode, and two bias posts with low pass filter(LPF). The cavity is designed for fundamental mode at 47 GHz and operated at second harmonic of 94 GHz center frequency. The developed waveguide VCO has 1.095 GHz bandwidth, 590 MHz linearity with 1.69% and output power from 14.86 to 15.93 dBm. The phase noise is under -95 dBc/Hz at 1 MHz offset.