• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.5
• /
• pp.1028-1033
• /
• 2014

We investigate the OFDM-based wireless LAN systems operating in the 60 GHz frequency band as part of the fourth-generation (4G) systems. The 60 GHz band is of much interest since this is the band in which a massive amount of spectral space has been allocated worldwide for dense wireless local communications. This paper gives an overview of 60 GHz band channel characteristics and an effect on phase noise. The performance of OFDM system is severely degraded by the local oscillator phase noise, which causes both common phase error and inter-carrier interference. In this paper, we apply phase noise suppression (PNS) algorithm that is easy for implementation to OFDM based 60 GHz wireless LAN system and analyze the SER performance. In case of using the PNS algorithm, SER performance is improved about 6 dB, 7.5 dB, respectively in 16, 64-QAM.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.12
• /
• pp.941-947
• /
• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.12
• /
• pp.84-89
• /
• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop dual split ring resonator is presented for reducing the phase noise. The square-shaped dual split ring resonator having the form of the microstrip square open loop is investigated to reduce the phase noise. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator as well as the conventional microstrip line resonator, the microstrip square dual split ring resonator has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of -123.2~-122.0 dBc/Hz @ 100 kHz in the tuning range, 11.74~11.75 GHz. The figure of merit (FOM) of this VCO is-214.8~-221.7 dBc/Hz dBc/Hz @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using microstrip square open loop resonator, the phase noise of VCO using the proposed resonator has been improved in 26 dB, 10 dB, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.541-546
• /
• 2010

The push-push DRO(dielectric resonator oscillator) using a multi-layer structure of LTCC(low temperature co-fired ceramic) fabrication is designed. After the single DRO of series feedback type in the center frequency of 8GHz is designed, the push-push DRO in the center frequency of 16GHz including the Wilkinson power combiner is designed. The bias circuit affecting the size of oscillator are embedded in the intermediate layer of the LTCC multi-layer substrate. As a result, the large reduction in the size of VCO is obtained compared to the general oscillator on the single layer substrate. Experimental results show that the fundamental and third harmonics suppression are above 15dBc and 25dBc, respectively, and phase noise characteristics of the push-push DRO presents performance of -102dBc/Hz@100KHz and -128dBc/Hz@1MHz offset frequencies from carrier.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.5
• /
• pp.2443-2448
• /
• 2013

In this paper, a design of size-reduced microwave oscillator using common defected ground structure (common DGS) is described. At first, an oscillator is designed using the normal stub resonator, and the conventional DGS patterns are inserted for the first trial of size-reduction. Finally, the DGS resonator section is folded by half size in order to adopt the common DGS, and this produces the proposed size-reduced oscillator. Common DGS pattern is inserted for a better size-reduction than when conventional DGSs are used. The folded transmission line is connected using the 3-dimensional signal via-holes. For an example of design, a 2.1GHz oscillator is designed and fabricated using a small signal transistor and common DGS, which shows the size-reduction of 11 mm. The measurement shows 6.7dBm of output power and -133dBc/Hz@1MHz of phase noise. The measured performances are so similar to those of the oscillators before size-reduction and prove the proposed size-reduction method of oscillators using common DGS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.9 no.6
• /
• pp.833-842
• /
• 1998

In this paper, a K-band oscillator which is composed of a hair-pin resonator, a GaAs MESFET, and a frequency doubler, is suggested, implemented by HMIC(Hybrid Microwave Integrated Circuits) form, and characterized for its microwave performance. A $\lambda_g$/4 open stub is used in frequency doubler to suppress the fundamental frequency of 9 GHz which is the output of the hair-pin resonator oscillator and output matching network is optimized for its second harmonic freuency of 18 HGz. For the oscillator, the output power of -0.83 dBm, the fundamental frequency suppression of -23 dBc, and phase noise of -86 dBc/Hz at 18.20 GHz are obtained.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.650-656
• /
• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.7
• /
• pp.18-27
• /
• 1997

A CMOS 950 MHz frequency synthesizer is designed and fabricated in a 0.8.mu.m standard CMOS process for IS-95-A CDMA mobile communication transceivers To utilize a CMOS ring VCO in a CDMA wireless communication receisver, we employed a QDC (quasi-direct conversion) receiver architecture for CDMA applications. Realized RF frequency synthesizer used as the RF local oscillator for a QDC receiver exhibits a phase noise of -92 dBc/Hz at 885kHz offset from the 950.4 MHz carrier, which complies with IS-95-A CDMA specification. It has a rms jitter of 23.7 ps, and draws 30mA from a 5V supply. Measured I/Q phase error of the 950.4 output signals is 0.7 degree.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2002.11a
• /
• pp.123-126
• /
• 2002

본 논문에서는 샘플링 위상검파를 이용하여 고안정 마이크로파발진기를 설계하고 3체배시켜 30㎓대의 발진기를 설계하였다. 설계된 발진기는 병렬귀환 유전체공진과, 바랙터 다이오드를 이용하여 전압제어하므로써 자유발진 신호를 안정화 시켰다. 발진기의 저위상/고안정 특성을 위하여 마이크로파 샘플링 위상 검파회로를 이용하여 출력 주파수를 저위상/고안정 특성을 가지게 하였다. 병렬귀환 유전체공진발진기에 의한 마이크로파 샘플링 위상동기발진기는 발진주파수 9.733㎓에서 10.17㏈m의 출력값을 보였으며 3체배된 29.2㎓ 발진기의 위상잡음은 -95㏈c/Hz @10KHz와 -105㏈c/Hz @100KHz의 우수한 특성을 나타내었다.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.890-893
• /
• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.