• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.

• Journal of the Optical Society of Korea
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• v.15 no.1
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• pp.1-3
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• 2011

We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• ETRI Journal
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• v.43 no.1
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• pp.64-73
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• 2021

Two-dimensional torus network nodes are typically interconnected using XY routing algorithm for transmitting a packet from a source node to a destination node. In XY routing, if all the paths are used efficiently, the throughput and latency can be improved. In this paper, to utilize all the paths efficiently, we propose a novel binary optical routing algorithm (BORA) to improve the throughput and latency. The throughput is calculated according to the injection rate and number of packets received at the destination. The XY routing algorithm and proposed BORA are implemented using objective modular network testbed in C++ simulation software and the results are analyzed and compared. In this paper, the simulation results show that the network latency reduces to 50% while using the proposed algorithm; moreover, the throughput is also improved.

• Korean Journal of Optics and Photonics
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• v.34 no.4
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• pp.151-156
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• 2023

We propose to implement cost-effectively a high-speed short-haul interconnect by transmitting a 200-Gb/s/λ two-channel optical time-division-multiplexed signal generated by a carrier-suppressed optical pulse, which improves the robustness of the multiplexed signal to chromatic dispersion. The multiplexed 200-Gb/s signal is generated in the transmitter by combining two 100-Gb/s 4-level pulse-amplitude-modulated signals (generated using the optical pulse and two Mach-Zehnder modulators). After the signal is transmitted over a fiber, it is amplified by a semiconductor optical amplifier and detected by a photodiode. The amplified spontaneous emission noise is eliminated by an optical band-pass filter. The transmitted signal is reconstructed by a 2 × 2 multiple-input multiple-output equalizer, which compensates for crosstalk. Due to the use of the carrier-suppressed optical pulse, the 200-Gb/s signal can be transmitted over fiber with a chromatic dispersion of 40 ps/nm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Journal of Korea Spatial Information System Society
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• v.7 no.2 s.14
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• pp.57-66
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• 2005

The Interconnecting Highways problem is an abstract of many practical Layout Design problems in the areas of VLSI design, the optical and wired network design, and the planning for the road constructions. For the road constructions, the shortest-length road layouts that interconnect existing positions will provide many more economic benefits than others. That is, finding new road layouts to interconnect existing roads and cities over a wide area is an important issue. This paper addresses an approximation scheme that finds near optimal road layouts for the Interconnecting Highways problem which is NP-hard. As long as computational resources are provided, the near optimality can be acquired asymptotically. This implies that the result of the scheme can be regarded as the optimal solution for the problem in practice. While other approximation schemes can be made for the problem, this proposed scheme provides a big merit that the algorithm designed by this scheme fits well to given problem instances.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1383-1385
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• 2005

We synthesized new poly(p -phenylene vinylene) (PPV) derivatives including different portions of crosslink that could interconnect the backbone of PPV for application in optoelectronic devices such as lightemitting-diodes, photovoltaic cells, and lasers. The fluorescence and electroluminescence properties of PPV including crosslink were discussed with respect of their structure and length of crosslink unit.