• Journal of the Optical Society of Korea
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• v.10 no.3
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• pp.130-142
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• 2006

Lab-on-a-chip technology is attracting great interest because the miniaturization of reaction systems offers practical advantages over classical bench-top chemical systems. Rapid mixing of the fluids flowing through a microchannel is very important for various applications of microfluidic systems. In addition, highly sensitive on-chip detection techniques are essential for the in situ monitoring of chemical reactions because the detection volume in a channel is extremely small. Recently, a confocal surface enhanced Raman spectroscopic (SERS) technique, for the highly sensitive biological analysis in a microfluidic sensor, has been developed in our research group. Here, a highly precise quantitative measurement can be obtained if continuous flow and homogeneous mixing condition between analytes and silver nano-colloids are maintained. Recently, we also reported a new analytical method of DNA hybridization involving a PDMS microfluidic sensor using fluorescence energy transfer (FRET). This method overcomes many of the drawbacks of microarray chips, such as long hybridization times and inconvenient immobilization procedures. In this paper, our recent applications of the confocal Raman/fluorescence microscopic technology to a highly sensitive lab-on-a-chip detection will be reviewed.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• Journal of Communications and Networks
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• v.11 no.1
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• pp.1-10
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• 2009

In this paper, we propose a chip-level detection and a spectral-slice scheme for the tunable-transmitter/fixed-receiver (TTFR)-based asynchronous spectral phase-encoded optical codedivision multiple-access (CDMA) system combined with timeencoding. The chip-level detection can enhance the tolerance of multiple access interference (MAI) because the channel collision does not occur as long as there is at least one weighted position without MAI. Moreover, the spectral-slice scheme can reduce the interference probability because the MAI with the different frequency has no adverse effects on the channel collision rate. As a result, these techniques mitigate channel collisions. We analyze the channel collision rate theoretically, and show that the proposed system can achieve a lower channel collision rate in comparison to both conventional systems with and without the time-encoding method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.269-274
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• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.319-322
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• 1999

In this paper, we report characteristics of a internal chip of LiNbO$_3$ modulator with low-driving-voltage at 150nm wavelength. A Ti diffusion method for LiNbO$_3$ optical waveguide and a buffer layer for improving phase velocity mismatch between optical and microwave waves were employed. The traveling-wave coplanar waveguide electrode of 35mm is used for reducing the driving voltage. From this work, wideband modulation of 10㎓ and low-driving voltage of 3.9volts are realized.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.111-116
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• 2007

A high power LED which is being used in many illumination applications as a new light source was simulated for its physical structure and then its optical properties were analyzed. To obtain accurate results from the designed LED model, properties of the die chip and reflector cup were varied. As a result, a high power LED model which has a radiation pattern of a Lambertian with its viewing angle of approximately $140^{\circ}$ and total included angle of $160^{\circ}$ was designed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.119-124
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• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.8-16
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• 2017

In this paper, we review studies attempting to triumph over the limitation of Si-based semiconductor technologies through a heterogeneous integration of high mobility compound semiconductors on a Si substrate, and the co-integration of electronic and/or optical devices. Many studies have been conducted on the heterogeneous integration of various materials to overcome the Si semiconductor performance and obtain multi-purpose functional devices. On the other hand, many research groups have invented device fusion technologies of electrical and optical devices on a Si substrate. They have co-integrated Si-based CMOS and InGaAs-based optical devices, and Ge-based electrical and optical devices. In addition, chip and wafer bonding techniques through TSV and TOV have been introduced for the co-integration of electrical and optical devices. Such intensive studies will continue to overcome the device-scaling limitation and short-channel effects of a MOS transistor that Si devices have faced using a heterogeneous integration of Si and a high mobility compound semiconductor on the same chip and/or wafer.