• 제목/요약/키워드: on-state drain current

검색결과 52건 처리시간 0.059초

Switching Characteristics of Amorphous GeSe TFT for Switching Device Application

  • 남기현;김장한;조원주;정홍배
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.403-404
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    • 2012
  • We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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Electrical Switching Characteristics of Thin Film Transistor with Amorphous Chalcogenide Channel

  • 남기현;김장한;정홍배
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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    • pp.280-281
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    • 2011
  • We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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자연 산화막과 엑시머 레이저를 이용한 Poly-Si/a-Si 이중 박막 다결정 실리콘 박막 트랜지스터 (Poly-Si Thin Film Transistor with poly-Si/a-Si Double Active Layer Fabricated by Employing Native Oxide and Excimer Laser Annealing)

  • 박기찬;박진우;정상훈;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제49권1호
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    • pp.24-29
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    • 2000
  • We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

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분석 조건에 따른 p-MOSFET의 게이트에 유기된 드레인 누설전류의 열화 (Degradation of Gate Induced Drain Leakage(GIDL) Current of p-MOSFET along to Analysis Condition)

  • 배지철;이용재
    • E2M - 전기 전자와 첨단 소재
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    • 제10권1호
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    • pp.26-32
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    • 1997
  • The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

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다결정 실리콘 박막 트랜지스터의 성능에 대한 채널 길이의 영향 (Influence of Channel Length on the Performance of Poly-Si Thin-Film Transistors)

  • 이정석;장창덕;백도현;이용재
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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    • pp.450-453
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    • 1999
  • In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

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Optically Controlled Silicon MESFET Modeling Considering Diffusion Process

  • Chattopadhyay, S.N.;Motoyama, N.;Rudra, A.;Sharma, A.;Sriram, S.;Overton, C.B.;Pandey, P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권3호
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    • pp.196-208
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    • 2007
  • An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

자기인지 신경회로망에서 아날로그 기억소자의 선형 시냅스 트랜지스터에 관한연구 (A Study on the Linearity Synapse Transistor of Analog Memory Devices in Self Learning Neural Network Integrated Circuits)

  • 강창수
    • E2M - 전기 전자와 첨단 소재
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    • 제10권8호
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    • pp.783-793
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    • 1997
  • A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

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자기인지 신경회로망에서 선형 시냅스 트랜지스터에 관한 연구 (A Study on the Linearity Synapse Transistor in Self Learning Neural Network)

  • 강창수;김동진;김영호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 하계학술대회 논문집
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    • pp.59-62
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    • 2000
  • A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

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PNP 게이트를 가지는 폴리 실리콘 박막 트랜지스터의 전기적 특성 (Electrical characteristics of polysilicon thin film transistors with PNP gate)

  • 민병혁;박철민;한민구
    • 전자공학회논문지A
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    • 제33A권3호
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    • pp.96-106
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    • 1996
  • One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

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Preparation of Epoxy/Organoclay Nanocomposites for Electrical Insulating Material Using an Ultrasonicator

  • Park, Jae-Jun;Park, Young-Bum;Lee, Jae-Young
    • Transactions on Electrical and Electronic Materials
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    • 제12권3호
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    • pp.93-97
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    • 2011
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.