• 전기전자학회논문지
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• 제21권3호
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• pp.272-275
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• 2017

최근 반도체의 집적도가 증가하고 배선 폭이 미세해짐에 따라 칩 수준의 EMI(electromagnetic interference)가 문제로 대두되고 있다. 이에 따라 칩 제조사는 칩 수준의 EMI를 측정하기 위해 TEM 셀(transverse electromagnetic cell)을 사용하고 있다. 이를 위해 측정용 PCB(printed circuit board)를 제작하여야 하지만, PCB의 배선 패턴 등이 EMI 측정에 영향을 미칠 수 있다는 점이 간과되고 있다. 본 논문에서는 PCB 설계 변수를 변화시켜가며 테스트 패턴을 제작한 다음 TEM 셀의 EMI 측정에 미치는 영향을 분석하였다. 또한 이를 바탕으로 EMI 측정에 미치는 영향을 최소화하기 위한 PCB 설계 가이드라인을 제시하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국재료학회지
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• 제22권9호
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• pp.454-458
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• 2012

Various adhesive materials are used in flip chip packaging for electrical interconnection and structural reinforcement. In cases of COF(chip on film) packages, low temperature bonding adhesive is currently needed for the utilization of low thermal resistance substrate films, such as PEN(polyethylene naphthalate) and PET(polyethylene terephthalate). In this study, the effects of anhydride and dihydrazide hardeners on the low-temperature snap cure behavior of epoxy based non-conductive pastes(NCPs) were investigated to reduce flip chip bonding temperature. Dynamic DSC(differential scanning calorimetry) and isothermal DEA(dielectric analysis) results showed that the curing rate of MHHPA(hexahydro-4-methylphthalic anhydride) at $160^{\circ}C$ was faster than that of ADH(adipic dihydrazide) when considering the onset and peak curing temperatures. In a die shear test performed after flip chip bonding, however, ADH-containing formulations indicated faster trends in reaching saturated bond strength values due to the post curing effect. More enhanced HAST(highly accelerated stress test) reliability could be achieved in an assembly having a higher initial bond strength and, thus, MHHPA is considered to be a more effective hardener than ADH for low temperature snap cure NCPs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• 전자공학회논문지A
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• 제33A권5호
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• 전자공학회논문지
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• 제51권11호
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• pp.83-93
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• 2014

최근 수년간 전기적 상호 연결 (electrical interconnect, EI) 기반 네트워크-온-칩 (Network-on-Chip, NoC) 에 대한 연구가 활발히 진행되고 있는 가운데, 궁극적으로 금속 배선은 대역폭, 응답 시간(latency), 전력 소모 등에서 물리적 한계에 직면할 것으로 예상된다. 실리콘 포토닉스(silicon photonics) 기술 발전으로 광학적 상호 연결(optical interconnect, OI)을 결합한 하이브리드 광학 네트워크-온-칩(Hybrid Optical NoC, HONoC)이 이러한 문제를 극복하기 위한 유망한 해결책으로 부각되고 있다. 한편 시스템-온-칩(System-on-Chip, SoC)은 높은 에너지 효율을 위하여 이기종 멀티 코어(Heterogeneous multi-core)로 구성되고 있어서 정형화된 토폴로지 기반 NoC 아키텍처의 확장이 필요하다. 본 논문에서는 타깃 애플리케이션 트래픽 특성을 고려한 에너지 및 응답 시간 최적화 하이브리드 광학 네트워크-온-칩의 토폴로지 설계 기법을 제안한다. 유전자 알고리즘을 이용하여 구현하였고, 실험 결과 평균 전력손실은 13.84%, 평균 응답 시간은 28.14% 각각 감소하였다.

• Journal of Welding and Joining
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• 제20권2호
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• pp.90-94
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• 2002

FC-BGA has advantages over other interconnection methods including high I/O counts, better electrical performance, high throughput, and low profile. But, FC-BGA has a lot of reliability issues. The 2nd level solder joint reliability of the FC-BGA with large chip on laminate substrate was studied in this paper. The purpose of this study is to discuss solder joint failures of 2nd level thermal cycling test. This work has been done to understand the influence of the structure of package, the properties of underfill, the properties and thickness of bismaleimide tiazine substrate and the temperature range of thermal cycling on 2nd level solder joint reliability. The increase of bismaleimide tiazine substrate thickness applied to low modulus underfill was improve of solder joint reliability. The resistance of solder ball fatigue was increased solder ball size in the solder joints of FC-BGA.

• 전자공학회논문지
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• 제53권7호
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• pp.131-137
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• 2016

본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다.