• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.844-853
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• 2008

This paper describes the design of a FEM(Front End Module) having power detection function for mobile handset application. The designed FEM consists of a MMIC(Monolithic Microwave Integrated Circuits) power amplifier chip, SAW Tx filter and duplexer, diode power detector and stripline matching circuit. An LTCC(Low Temperature Co-fired Ceramics) technology is adopted for miniaturized FEM. The frequency band is $824{\sim}869$ MHz which is the uplink Tx band of the CDMA mobile system. The size of designed FEM is $7.0{\times}5.5{\times}1.5\;mm^3$, which is an ultra-small size even though the power detector circuit is included. All sub-components of FEM have been developed and measured in advance before being integrated into FEM. The measured output power and gain are 27 dBm and 27 dB, respectively. In addition, the measured ACPR characteristics are 46.59 dBc and 55.5 dBc at 885 kHz and 1.98 MHz offset, respectively.

• Smart Media Journal
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• v.9 no.4
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• pp.102-108
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• 2020

In this paper, we propose a real-time method of detecting hand motions and extracting the signal frame induced by EF(Electric Field) sensors. The signal induced by hand motion includes not only noises caused by various environmental sources as well as sensor's physical placement, but also different initial off-set conditions. Thus, it has been considered as a challenging problem to detect the motion signal and extract the motion frame automatically in real-time. In this study, we remove the PLN(Power Line Noise) using LPF with 10Hz cut-off and successively apply MA(Moving Average) filter to obtain clean and smooth input motion signals. To sense a hand motion, we use two thresholds(positive and negative thresholds) with offset value to detect a starting as well as an ending moment of the motion. Using this approach, we can achieve the correct motion detection rate over 98%. Once the final motion frame is determined, the motion signals are normalized to be used in next process of classification or recognition stage such as LSTN deep neural networks. Our experiment and analysis show that our proposed methods produce better than 98% performance in correct motion detection rate as well as in frame-matching rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.681-689
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• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.527-536
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• 2000

This paper discusses the design of self-oscillating mixer type low noise down converter using the microwave field effect transistor. The mixer is consists of local oscillator in which high stability dielectric resonator and band pass filter to get rid of spurious oscillation at intermediate frequency stage. The microstrip antenna was integrated in the same substrate which generate 12.3GHz and low noise amplifier was also added after antenna using 3 stage of high electron mobility transistors. The output frequency from the local oscillator was chosen as 11.3GHz for the Ku-band application. The measured phase noise was -804dBc/Hz at 100kHz offset frequency, and the gain was 7～12dB in frequency range from 12.0GHz to 12.7GHz. The noise figure at intermediate frequency stage was 64H. The designed model shows less conversion loss than previous diode type mixer. The proposed mixer can be used in digital satellite broadcasting and communication system and expected to use in next generation low noise block design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of Power Electronics
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• v.13 no.3
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• pp.369-380
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• 2013

Direct torque control based on space vector modulation (SVM-DTC) protects the DTC transient merits. Furthermore, it creates better quality steady-state performance in a wide speed range. The modified method of DTC using SVM improves the electrical magnitudes of asynchronous machines, such as minimizing the stator current distortions, the stator flux with electromagnetic torque without ripple, the fast response of the rotor speed, and the constant switching frequency. In this paper, the proposed method is based on two new control strategies for direct torque control with space vector modulation. First, fuzzy logic control is used instead of the PI torque and a PI flux controller to minimizing the torque error and to achieve a constant switching frequency. The voltages in the direct and quadratic reference frame ($V_d$, $V_q$) are achieved by fuzzy logic control. In this scheme, the switching capability of the inverter is fully utilized, which improves the system performance. Second, the close loop of stator flux estimation based on the voltage model and a low pass filter is used to counteract the drawbacks in the open loop of the stator flux such as the problems saturation and dc drift. The response of this new control strategy is compared with DTC-SVM. The experimental and simulation results demonstrate that the proposed control topology outperforms the conventional DTC-SVM in terms of system robustness and eliminating the bad outcome of dc-offset.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.