• Title/Summary/Keyword: nitride residue

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A Study on the Nitride Residue and Pad Oxide Damage of Shallow Trench Isolation(STI)-Chemical Mechanical Polishing(CMP) Process (STI-CMP 공정의 질화막 잔존물 및 패드 산화막 손상에 대한 연구)

  • Lee, U-Seon;Seo, Yong-Jin;Kim, Sang-Yong;Jang, Ui-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.50 no.9
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    • pp.438-443
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    • 2001
  • In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

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A Study of Chemical Mechanical Polishing on Shallow Trench Isolation to Reduce Defect (CMP 연마를 통한 STI에서 결함 감소)

  • 백명기;김상용;김창일;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.501-504
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    • 1999
  • In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

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Effects of Trench Depth on the STI-CMP Process Defects (트랜치 깊이가 STI-CMP 공정 결함에 미치는 영향)

  • 김기욱;서용진;김상용
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.4
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    • pp.17-23
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    • 2002
  • The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

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A Study on the Reliability and Reproducibility of 571 CMP process (STI CMP 공정의 신뢰성 및 재현성에 관한 연구)

  • 정소영;서용진;김상용;이우선;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.25-28
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    • 2001
  • Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

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Analysis on the defect and scratch of Chemical Mechanical Polishing Process (CMP 공정의 Defect 및 Scratch의 유형분석)

  • Kim, Hyung-Gon;Kim, Chul-Bok;Kim, Sang-Yong;Lee, Cheol-In;Kim, Tae-Hyung;Chang, Eui-Goo;Seo, Yong-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.189-192
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    • 2001
  • Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

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Analysis on the defect and scratch of Chemical Mechanical Polishing process (CMP 공정의 Defect 및 Scratch의 유형분석)

  • 김형곤;김철복;정상용;이철인;김태형;장의구;서용진
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
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    • pp.189-192
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    • 2001
  • Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

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Removal of Post Etch/Ash Residue on an Aluminum Patterned Wafer Using Supercritical CO2 Mixtures with Co-solvents and Surfactants: the Removal of Post Etch/Ash Residue on an Aluminum Patterned Wafer

  • You, Seong-sik
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.2
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    • pp.55-60
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    • 2017
  • The supercritical $CO_2$ (sc-$CO_2$) mixture and the sc-$CO_2$-based Photoresist(PR) stripping(SCPS) process were applied to the removal of the post etch/ash PR residue on aluminum patterned wafers and the results were observed by scanning of electron microscope(SEM). In the case of MDII wafers, the carbonized PR was able to be effectively removed without pre-stripping by oxygen plasma ashing by using sc-$CO_2$ mixture containing the optimum formulated additives at the proper pressure and temperature, and the same result was also able to be obtained in the case of HDII wafer. It was found that the efficiency of SCPS of ion implanted wafer improved as the temperature of SCPS was high, so a very large amount of MEA in the sc-$CO_2$ mixture could be reduced if the temperature could be increased at condition that a process permits, and the ion implanted photoresist(IIP) on the wafer was able to be removed completely without pre-treatment of plasma ashing by using the only 1 step SCPS process. By using SCPS process, PR polymers formed on sidewalls of metal conductive layers such as aluminum films, titanium and titanium nitride films by dry etching and ashing processes were removed effectively with the minimization of the corrosion of the metal conductive layers.

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Chemical Mechanical Polishing Characteristics with Different Slurry and Pad (슬러리 및 패드 변화에 따른 기계화학적인 연마 특성)

  • 서용진;정소영;김상용
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.10
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    • pp.441-446
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    • 2003
  • The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

A Study for the Improvement of Torn Oxide Defects in Shallow Trench Isolation-Chemical Mechanical Polishing (STI-CMP) Process (STI--CMP 공정에서 Torn oxide 결함 해결에 관한 연구)

  • 서용진;정헌상;김상용;이우선;이강현;장의구
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.1
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    • pp.1-5
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    • 2001
  • STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

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