• 제목/요약/키워드: new memory

검색결과 1,699건 처리시간 0.03초

Migration Policies of a Main Memory Index Structure for Moving Objects Databases

  • An Kyounghwan;Kim Kwangsoo
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2004년도 Proceedings of ISRS 2004
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    • pp.673-676
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    • 2004
  • To manage and query moving objects efficiently in MMDBMS, a memory index structure should be used. The most popular index structure for storing trajectories of moving objects is 3DR-tree. The 3DR-tree also can be used for MMDBMS. However, the volume of data can exceed the capacity of physical memory since moving objects report their locations continuously. To accommodate new location reports, old trajectories should be migrated to disk or purged from memory. This paper focuses on migration policies of a main memory index structure. Migration policies consist of two steps: (i) node selection, (ii) node placement. The first step (node selection) selects nodes that should be migrated to disk. The criteria of selection are the performance of insertion or query. The second step (node placement) determines the order of nodes written to disk. This step can be thought as dynamic declustering policies.

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Linked-list 구조를 갖는 ATM용 공통 버퍼형 메모리 스위치 설계 (Design of a shared buffer memory switch with a linked-list architecture for ATM applications)

  • 이명희;조경록
    • 한국통신학회논문지
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    • 제21권11호
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    • pp.2850-2861
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    • 1996
  • This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

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다중 블록 지우기 기능을 적용한 퓨전 플래시 메모리의 FTL 성능 측정 도구 설계 및 구현 (Design and Implementation of FTL Performance Measurement Tool using Multi Block Erase of Fusion Flash Memory)

  • 이동환;조원희;김덕환
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.647-648
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    • 2008
  • Traditional FTL and flash file systems based of NAND flash memory may not be adaptively applied to new fusion flash memory which combines the advantages of NAND and NOR flash memory. In this paper, we propose a FTL performance measurement tool using Multi Block Erase function of fusion flash memory. The performance measurement tool shows that multi block erase function can be effectively utilized in performance enhancement of garbage collection for fusion flash memory.

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계층 비트라이에 의한 최적 페이지 인터리빙 메모리 (An Optimum Paged Interleaving Memory by a Hierarchical Bit Line)

  • 조경연;이주근
    • 대한전자공학회논문지
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    • 제27권6호
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    • pp.901-909
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    • 1990
  • With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

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터널링 메커니즘을 이용한 메모리 소자 연구 (A Study of Memory Device based on Tunneling Mechanism)

  • 이준하
    • 반도체디스플레이기술학회지
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    • 제5권1호
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    • pp.17-20
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    • 2006
  • This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

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The Improvement of the Data Overlapping Phenomenon with Memory Accessing Mode

  • Yang, Jin-Wook;Woo, Doo-Hyung;Kim, Dong-Hwan;Yi, Jun-Sin
    • Journal of Information Display
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    • 제9권1호
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    • pp.6-13
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    • 2008
  • Mobile phones use the embedded memory in LDI (LCD Driver IC). In memory accessing mode, data overlapping phenomenon can occur. These days, various contents such as DMB, Camera, Game are merged to phone. Accordingly, with more data transmission, there would be more data overlapping phenomenon in memory accessing mode. Human eyes perceive this data overlapping phenomenon as simply horizontal line noise. The cause of the data overlapping phenomenon was analysed in this paper. The data overlapping phenomenon can be changed by the speed of data transmission between the host and LDI. The optimum memory accessing position can be defined. This paper proposes a new algorithm for avoiding data overlapping.

Mechanical Behavior of Shape Memory Fibers Spun from Nanoclay-Tethered Polyurethanes

  • Hong, Seok-Jin;Yu, Woong-Ryeol;Youk, Ji-Ho
    • Macromolecular Research
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    • 제16권7호
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    • pp.644-650
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    • 2008
  • This study examined the effect of nanoclays on the shape memory behavior of polyurethane (PU) in fibrous form. A cation was introduced into the PU molecules to disperse the organo-nanoclay (MMT) into poly($\varepsilon$-caprolactone) (PCL)-based PU (PCL-PU). The MMT/PCL-PU nanocomposites were then spun into fibers through melt-processing. The shape memory performance of the spun fibers was examined using a variety of thermo-mechanical tests including a new method to determine the transition temperature of shape memory polymers. The MMTs showed an improved the fixity strain rate of the MMT /PCL- PU fibers but a slight decrease in their recovery strain rate. This was explained by the limited movement of PU molecules due to the presence of nanoclays. The shape memory performance of the MMT/PCL-PU fibers was not enhanced significantly by the nanoclays. However, their recovery power was improved significantly up to a strain of approximately 50%.

A Finite Memory Filter for Discrete-Time Stochastic Linear Delay Systems

  • Song, Il Young;Song, Jin Mo;Jeong, Woong Ji;Gong, Myoung Sool
    • 센서학회지
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    • 제28권4호
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    • pp.216-220
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    • 2019
  • In this paper, we propose a finite memory filter (estimator) for discrete-time stochastic linear systems with delays in state and measurement. A novel filtering algorithm is designed based on finite memory strategies, to achieve high estimation accuracy and stability under parametric uncertainties. The new finite memory filter uses a set of recent observations with appropriately chosen initial horizon conditions. The key contribution is the derivation of Lyapunov-like equations for finite memory mean and covariance of system state with an arbitrary number of time delays. A numerical example demonstrates that the proposed algorithm is more robust and accurate than the Kalman filter against dynamic model uncertainties.

Memory Allocation in Mobile Multitasking Environments with Real-time Constraints

  • Hyokyung, Bahn
    • International Journal of Internet, Broadcasting and Communication
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    • 제15권1호
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    • pp.79-84
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    • 2023
  • Due to the rapid performance improvement of smartphones, multitasking on mobile platforms has become an essential feature. Unlike traditional desktop or server environments, mobile applications are mostly interactive jobs where response time is important, and some applications are classified as real-time jobs with deadlines. When interactive and real-time jobs run concurrently, memory allocation between multitasking applications is a challenging issue as they have different time requirements. In this paper, we study how to allocate memory space when real-time and interactive jobs are simultaneously executed in a smartphone to meet the multitasking requirements between heterogeneous jobs. Specifically, we analyze the memory size required to satisfy the constraints of real-time jobs and present a new model for allocating memory space between heterogeneous multitasking jobs. Trace-driven simulations show that the proposed model provides reasonable performance for interactive jobs while guaranteeing the requirement of real-time jobs.

Design of an Efficient In-Memory Journaling File System for Non-Volatile Memory Media

  • Hyokyung Bahn
    • International journal of advanced smart convergence
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    • 제12권1호
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    • pp.76-81
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    • 2023
  • Journaling file systems are widely used to keep file systems in a consistent state against crash situations. As traditional journaling file systems are designed for block I/O devices like hard disks, they are not efficient for emerging byte-addressable NVM (non-volatile memory) media. In this article, we present a new in-memory journaling file system for NVM that is different from traditional journaling file systems in two respects. First, our file system journals only modified portions of metadata instead of whole blocks based on the byte-addressable I/O feature of NVM. Second, our file system bypasses the heavy software I/O stack while journaling by making use of an in-memory file system interface. Measurement studies using the IOzone benchmark show that the proposed file system performs 64.7% better than Ext4 on average.