• Journal of Life Science
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• v.26 no.2
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• pp.234-240
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• 2016

The Y-maze is widely used to test working memory in behavioral science. For this purpose, spontaneous alternation behavior is monitored, and an increased percentage of spontaneous alternation is regarded as enhanced working memory. However, in some cases, the percentage of spontaneous alternation does not accurately reflect the extent of working memory in rodents. To complement the short-comings of this measure, we developed a new method to evaluate working memory on the Y-maze. This is done by defining all spontaneous alternation cases and P_i, the probability that the rodent achieved spontaneous alternation from each alternation case. After all P_i-values acquired in each animal are summarized, the result is considered as entropy. To validate the new analytical method, mice were raised under either control or an enriched environmental condition for 10 weeks, and working memory behavior on the Y-maze was monitored. The results showed that the new analytical method successfully reproduced significance. In addition, the new method turned out to be more accurate than measurement of the percentage of spontaneous alternation, meaning that, to get higher entropy, alternation should be recorded in all arms and directions. Together, these data indicate that the new analytical method is a useful supplement to the method that compares the percentage of spontaneous alternation, and thus is a good tool with which to evaluate working memory in rodents.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Sleep Medicine and Psychophysiology
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• v.4 no.1
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• pp.15-28
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• 1997

Longterm memory is encoded in the neuronal connectivities of the brain. The most successful models of human memory in their operations are models of distributed and self-organized associative memory, which are founded in the principle of simulaneous convergence in network formation. Memory is not perceived as the qualities inherent in physical objects or events, but as a set of relations previously established in a neural net by simultaneousy occuring experiences. When it is easy to find correlations with existing neural networks through analysis of network structures, memory is automatically encoded in cerebral cortex. However, in the emergence of informations which are complicated to classify and correlated with existing networks, and conflictual with other networks, those informations are sent to the subcortex including hippocampus. Memory is stored in the form of templates distributed across several different cortical regions. The hippocampus provides detailed maps for the conjoint binding and calling up of widely distributed informations. Knowledge about the distribution of correlated networks can transform the existing networks into new one. Then, hippocampus consolidats new formed network. Amygdala may enable the emotions to influence the information processing and memory as well as providing the visceral informations to them. Cortico-striatal-pallido-thalamo-cortical loop also play an important role in memory function with analysis of language and concept. In case of difficulty in processing in spite of parallel process of informations, frontal lobe organizes theses complicated informations of network analysis through temporal processing. With understanding of brain mechanism of memory and information processing, the brain mechanism of mental phenomena including psychopathology can be better explained in terms of neurobiology and meuropsychology.

• Journal of Broadcast Engineering
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• v.27 no.4
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• pp.561-568
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• 2022

Most deep learning-based video object segmentation methods perform the segmentation with past prediction information stored in external memory. In general, the more past information is stored in the memory, the better results can be obtained by accumulating evidence for various changes in the objects of interest. However, all information cannot be stored in the memory due to hardware limitations, resulting in performance degradation. In this paper, we propose a method of storing new information in the external memory without additional memory allocation. Specifically, after calculating the attention score between the existing memory and the information to be newly stored, new information is added to the corresponding memory according to each score. In this way, the method works robustly because the attention mechanism reflects the object changes well without using additional memory. In addition, the update rate is adaptively determined according to the accumulated number of matches in the memory so that the frequently updated samples store more information to maintain reliable information.

• Journal of applied mathematics & informatics
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• v.24 no.1_2
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• pp.367-376
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• 2007

In this paper we consider the global convergence of a new super memory gradient method for unconstrained optimization problems. New trust region radius is proposed to make the new method converge stably and averagely, and it will be suitable to solve large scale minimization problems. Some global convergence results are obtained under some mild conditions. Numerical results show that this new method is effective and stable in practical computation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4B
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• pp.397-402
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• 2004

In this paper, we have designed and simulated a new file transmission method. This method restricts memory copy and context switching happened in traditional file transmission. This method shows an improved performance than traditional method in network environment. When the UNIX/LINUX system that uses the existing file transfer technique transmits a packet to the remote system, a memory copy between the user and kernel space occurs over twice at least. Memory copy between the user and kernel space increase a file transmission time and the number of context switching. As a result, the existing file transfer technique has a problem of deteriorating the performance of file transmission. We propose a new algorithm for solving these problems. It doesn't perform memory copy between the user and kernel space. Hence, the number of memory copy and context switching is limited to the minimum. We have modified the network related source code of LINUX kernel 2.6.0 to analyzing the performance of proposed algorithm and implement new network system calls.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.