• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.1896-1900
• /
• 2003

In this paper, a new type of output feedback control, called a receding horizon finite memory control (RHFMC), is proposed for stochastic discrete-time state space systems. Constraints such as linearity and finite memory structure with respect to an input and an output, and unbiasedness from the optimal state feedback control are required in advance. The proposed RHFMC is chosen to minimize an optimal criterion with these constraints. The RHFMC is obtained in an explicit closed form using the output and input information on the recent time interval. It is shown that the RHFMC consists of a receding horizon control and an FIR filter. The stability of the RHFMC is investigated for stochastic systems.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.6
• /
• pp.293-302
• /
• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• International Journal of Contents
• /
• v.3 no.1
• /
• pp.19-23
• /
• 2007

Recently, several main-memory index structures have been proposed to reduce the impact of secondary cache misses. In mainmemory storage systems, secondary cache misses have a substantial effect on the performance of index structures. However, recent studies still stiffer from secondary cache misses when visiting each level of index tree. In this paper, we propose a new index structure that minimizes the total amount of cache miss latency. The proposed index structure prefetched grandchildren of a current node. The basic structure of the proposed index structure is based on that of the CSB+-Tree, which uses the concept of a node group to increase fan-out. However, the insert algorithm of the proposed index structure significantly reduces the cost of a split. The superiority of our algorithm is shown through performance evaluation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.3
• /
• pp.170-172
• /
• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.5
• /
• pp.19-32
• /
• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Smart Structures and Systems
• /
• v.14 no.4
• /
• pp.541-558
• /
• 2014

This paper proposes a new design of shape memory alloy (SMA) wire actuated gripper for open mode operation. SMA can generate smooth muscle movements during actuation which make them potentially good contenders in designing grippers. The principle of the shape memory alloy gripper is to convert the linear displacement of the SMA wire actuator into the angular displacement of the gripping jaw. Steady state analysis is performed to design the wire diameter of the bias spring for a known SMA wire. The gripper is designed to open about an angle of $22.5^{\circ}$ when actuated using pulsating electric current from a constant current source. The safe operating power range of the gripper is determined and verified theoretically. Experimental evaluation for the uncontrolled gripper showed a rotation of $19.97^{\circ}$. Forced cooling techniques were employed to speed up the cooling process. The gripper is simple and robust in design (single movable jaw), easy to fabricate, low cost, and exhibits wide handling capabilities like longer object handling time and handling wide sizes of objects with minimum utilization of power since power is required only to grasp and release operations.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.2 no.4
• /
• pp.260-273
• /
• 2007

The wireless sensor network (WSN) nodes are required to operate for several months with the limited system resource such as memory and power. The hardware platform of WSN has 128Kbyte program memory and 8Kbytes data memory. Also, WSN node is required to operate for several months with the two AA size batteries. The MAC, Network protocol, and small application must be operated in this WSN platform. We look around the problem of memory and power for WSN requirements. Then, we propose a new computing model of system software for WSN node. It is the Atomic Object Model (AOM) with Dual Priority Scheduling. For the verification of model, we design and implement IEEE 802.15.4 MAC protocol with the proposed model.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.421-425
• /
• 1999

As the market size of multiprocessor systems for commercial applications, parallel systems, especially cache-coherent shared-memory multiprocessors that are conventionally designed for scientific applications need to be tuned in different fashion to achieve the best performance for new application area. In this paper, indepth investigation on the memory behavior which is the primary cause for performance changes were made. We chose representative benchmarks in scientific and commercial application areas. After running execution-driven simulation for bus-based cache-coherent shared-memory multiprocessors, we experienced significant differences and conclude that the systems must be carefully and differently designed to achieve the best performance when they are built for distinct applications.

• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.267-269
• /
• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes.

• Smart Structures and Systems
• /
• v.7 no.3
• /
• pp.185-198
• /
• 2011

The promise of biomimetic smart structures that can function as sensors and actuators in biomedicine is enormous. Technological development in the field of stimuli-responsive shape memory polymers have opened up a new avenue of applications for polymer-based synthetic actuators. Such synthetic actuators mimic various attributes of living organisms including responsiveness to stimuli, shape memory, selectivity, motility, and organization. This article briefly reviews various stimuli-responsive shape memory polymers and their application as bioactuators. Although the technological advancements have prototyped the potential applications of these smart materials, their widespread commercialization depends on many factors such as sensitivity, versatility, moldability, robustness, and cost.