• ETRI Journal
• /
• v.31 no.2
• /
• pp.209-214
• /
• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1997.10a
• /
• pp.454-457
• /
• 1997

The purpose of this study is to develop an optimal model, using existing models, that is able to estimate the amount of spatter utilizing artificial neural network in the short circuit transfer mode of gas metal arc (GMA) welding. The amount of spatter generated during welding can become a barometer which represents the process stability of metal transfer in GMA welding, and it depends on some factors which constitute a periodic waveforms of welding current and arc voltage in short circuit GMA welding. So, the 12 factors, which could express the characteristics for the waveforms, and the amount of spatter are used as input and output variables of the neural network, respectively. Two neural network models to estimate the amount of spatter are proposed: A neural network model, where arc extinction is not considered, and a combined neural network model where it is considered. In order to reduce the calculation time it take to produce an output, the input vector and hidden layers for each model are optimized using the correlation coefficients between each factor and the amount of spattcr. The est~mation performance of each optimized model to the amount of spatter IS assessed and compared to the est~mation performance of the model proposed by Kang. Also, through the evaluation for the estimation performance of each optimized model, it is shown that the combined neural network model can almost perfectly predict the amount of spatter.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.254-257
• /
• 1993

This paper presents a new method to implement Hebbian learning method on artificial neural network. In hebbian learning algorithm, complexity in terms of multiplications is high. To save the chip area, we consider a new learning circuit. By calculating similarity, or correlation between $X_i$ and $O_i$, large portion of circuits commonly used in conventional neural networks is not necessary for this new hebbian learning circuit named COR. The output signals of COR is applied to weight storage capacitors for direct control the voltages of the capacitors. The weighted sum, ${\Sigma}W_{ij}O_j$, is realized by multipliers, whose output currents are summed up in one line which goes to learning circuit or output circuit. The drain current of the multiplier can produce positive or negative synaptic weights. The pass transistor selects eight learning mode or recall mode. The layout of an learnable six-neuron fully connected Hopfield neural network is designed, and is simulated using PSPICE. The network memorizes, and retrieves the patterns correctly under the existence of minor noises.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.3
• /
• pp.1138-1143
• /
• 2015

Effects of fabrication process variations on impedance of microelectrodes integrated on a neural probe were examined through equivalent circuit modeling and SPICE simulation. Process variation and the corresponding range were estimated based on experimental data. The modeling results illustrate that the process variation induced by metal etching process was the dominant factor in impedance variation. We also demonstrate that the effect of process variation is frequency dependent. Another process variation that was examined in this work was the thickness variation induced by deposition process. The modeling results indicate that the effect of thickness variation on impedance is negligible. This work provides a means to predict the variations in impedance values of microelectrodes on neural probe due to different process variations.

• Applied Microscopy
• /
• v.46 no.2
• /
• pp.100-104
• /
• 2016

Electron microscopy is currently the only available technique with a spatial resolution sufficient to identify fine neuronal processes and synaptic structures in densely packed neuropil. For large-scale volume reconstruction of neuronal connectivity, serial block-face scanning electron microscopy allows us to acquire thousands of serial images in an automated fashion and reconstruct neural circuits faster by reducing the alignment task. Here we introduce the whole reconstruction procedure of synaptic network in the rat hippocampal CA1 area and discuss technical issues to be resolved for improving image quality and segmentation. Compared to the serial section transmission electron microscopy, serial block-face scanning electron microscopy produced much reliable three-dimensional data sets and accelerated reconstruction by reducing the need of alignment and distortion adjustment. This approach will generate invaluable information on organizational features of our connectomes as well as diverse neurological disorders caused by synaptic impairments.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.62-71
• /
• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.1
• /
• pp.13-22
• /
• 1991

In this paper we designed 2 bit ECC(Error Checking and Correction) circuit using Single Layer Perceptron type neural networks. We used (11, 6) block codes having 6 data bits and 8 check bits with appling cyclic hamming codes. All of the circuits are layouted by CMOs 2um double metal design rules. In the result of circuit simulation, 2 bit ECC circuit operates at 67MHz of input frequency.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.501-503
• /
• 1993

A circuit of sigmoid function for neural network is designed by using Piecewise Linear (PWL) method. The slope of sigmoid function can be adjusted to 2 and 0.25. Also the circuit presents both sigmoid function and its differential form. The circuits is simulated by using ViewLogic. Theoretical and simulated performance agree with 1.8 percent.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.1033-1036
• /
• 1999

This paper proposes an efficient fault diagnosis for digital circuits using multilayer neural networks. The efficient learning algorithm is also proposed for the multilayer neural network, which is combined the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The fault-diagnosis system using the multilayer neural network of the proposed algorithm has been applied to the parity generator circuit. The simulation results shows that the proposed system is higher convergence speed and rate, in comparision with system using the backpropagation algorithm based on the gradient descent.

• Nuclear Engineering and Technology
• /
• v.55 no.6
• /
• pp.2125-2138
• /
• 2023

The printed circuit heat exchanger (PCHE) with airfoil fins has the benefits of high compactness, high efficiency and superior heat transfer performance. A novel multi-objective optimization approach is presented to design the airfoil fin PCHE in this paper. Three optimization design variables (the vertical number, the horizontal number and the staggered number) are obtained by means of dimensionless airfoil fin arrangement parameters. And the optimization objective is to maximize the Nusselt number (Nu) and minimize the Fanning friction factor (f). Firstly, in order to investigate the impact of design variables on the thermal-hydraulic performance, a parametric study via the design of experiments is proposed. Subsequently, the relationships between three optimization design variables and two objective functions (Nu and f) are characterized by an improved particle swarm optimization-backpropagation artificial neural network. Finally, a multi-objective optimization is used to construct the Pareto optimal front, in which the non-dominated sorting genetic algorithm II is used. The comprehensive performance is found to be the best when the airfoil fins are completely staggered arrangement. And the best compromise solution based on the TOPSIS method is identified as the optimal solution, which can achieve the requirement of high heat transfer performance and low flow resistance.