• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.2
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• pp.112-117
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• 2012

This paper presents a new stopper mechanism for precision stage by using the Piezoelectric element actuator. The new stage including a new stopper mechanism has the precision positioning mechanism that was been developed for generation displacements with nanometer accuracy and a millimeter dynamic range simulataneouly. The stage is composed not of the mechanical two stopper but of only one Piezoelectric element actuator. The characteristics for the new stage and the stopper have been evaluated experimentally. As the results, we can know that the linearity error characteristics of stage is 30nm in the $20{\mu}m$ measurement range. In addition, the experimental results are confirmed the possibility of the movement in millimeter range.

• Journal of KSNVE
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• v.9 no.6
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• pp.1227-1233
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• 1999

Modern technology depends on the reliability of extremely high technology equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a nanometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. This paper deals with the structural dynamic design in high class semiconductor factory in order to be satisfied more strict vibration criteria for high sensitive equipment.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.7 s.184
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• International Journal of Precision Engineering and Manufacturing
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• v.7 no.4
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• pp.18-22
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• 2006

Although many efforts have been made in making nanometer-sized holes, there is still a major challenge in fabricating individual single-digit nanometer holes in a more controllable way for different materials, size distribution and hole shapes. In this paper we describe our efforts to use a top down approach in nanofabrication method to make single-digit nanoholes. There are three major steps towards the fabrication of a single-digit nanohole. 1) Preparing the freestanding thin film by epitaxial deposition and electrochemical etching. 2) Making sub-micro holes ($0.2{\mu}\;to\;0.02{\mu}$) by focused ion beam (FIB), electron beam (EB), atomic force microscope (AFM), and others methods. 3) Reducing the hole size to less than 10 nm by epitaxial deposition, FIB or EB induced deposition and micro coating. Preliminary work has been done on thin films (30 nm in thickness) preparation, sub-micron hole fabrication, and E-beam induced deposition. The results are very promising.

• Journal of environmental and Sanitary engineering
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• v.13 no.3
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• pp.72-78
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• 1998

For investigation into gas permeation characteristics, the porous alumina membrane with asymmetrical structure, having upper layer with 10 nanometer under of pore diameter and lower layer with 36 nanometer of pore diameter, was prepared by anodic oxidation using DC power supply of constant current mode in an aqueous solution of sulfuric acid. The aluminium plate was pre-treated with thermal oxidation, chemical polishing and electrochemical polishing before anodic oxidation. Because the pore size depended upon the electrolyte, electrolyte concentration, temperature, current density, and so on, the the membranes were prepared by controling the current density, as a very low current density for upper layer of membrane and a high current density for lower layer of membrane. By control of current quantity, the thicknesses of upper layer of membranes were about $6{\;}{\mu}m$ and the total thicknesses of membranes were about $80-90{\;}{\mu}m$. We found that the mechanism of gas permeation depended on model of the Knudsen flow for the membrane prepared at each condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.131-134
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• 1998

This work was carried out to develop a pattern on the nanometer scale using plasma polymerization and plasma etching. This study is also aimed at developing a resist for the nano process and a vacuum lithography process. The thin films of plasma polymerization were fabricated by the plasma po1ymerization of inter-electrode capacitively coupled gas flow system. After delineating the pattern at accelerating voltage of 30[kV]. ranging the dose of 1∼500[${\mu}$C/$\textrm{cm}^2$], the pattern was developed with dry tree and formed by plasma etching. By analysing of the molecule structure using FT-lR, it was confirmed that the thin films of PPMST contains the functional radicals of the MST monomer. The thin films of PPMST had a highly crosslinked structure resulting in a higher molecule weight than the conventional resist.

• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.93-98
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• 2013

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. To successfully imprint a nanosized pattern with the thermal NIL, the process conditions such as temperature and pressure should be appropriately selected. This starts with a clear understanding of polymer material behavior during the thermal NIL process. In this paper, a filling process of the polymer resist into nanometer scale cavities during the thermal NIL at the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer. In the simulation, the filling process and the residual layer formation are numerically investigated. And the effects of pressure and temperature on NIL process, specially the residual layer formation are discussed.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.29-33
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• 2002

Various nanometer-scale structures are fabricated on hydrogen-passivated p-type Si(100) surface by scanning probe microscopy(SPM). The hydrogen-passivation is performed by dipping the samples in diluted 10% HF solution for one min.. Pt alloy wires are used for tips and the tips are made by cutting the wires at 45$^{\circ}$ slanted. Various line features are fabricated in various bias voltage. The optimal structure is the line of about 30 nm width on 1.7V bias voltage and 1 nA tunneling current.  

• Journal of the Korean Ceramic Society
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• v.37 no.11
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• pp.1078-1083
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• 2000

정전안정화 및 입체안정화를 동시에 적용한 복합안정화기구에 의하여 25 부피%의 나노 $Al_2$O$_3$슬러리를 제조하고, 이로부터 얻은 주입성형체, 원심성형체, 진공성형체의 기공구조 분석을 통하여 입자충전거동을 살펴보았다. 나노 알루미나 분말의 습식 성형체의 충전구조는 성형방법에 의하여 가해지는 외력의 영향을 크게 받지만, 반발력을 제공하는 표면장벽층의 상호작용에 의해서도 현저한 차이를 보이는 것으로 나타났다. 예비소결실험을 통하여 나노분말에서도 기공크기가 작고, 크기분포가 좁으며, 높은 밀도를 가진 균일성형체의 미세구조가 소결미세구조를 균일하게 하는데 필수적인 조건임을 확인하였다.