• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• Korean Journal of Optics and Photonics
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• v.32 no.5
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• pp.209-214
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• 2021

High-power continuous-wave operation of a Yb-doped double-clad fiber laser at 1018 nm, pumped by high-power diode lasers at 976 nm, is reported. Based on numerical calculation of the gain and laser signal power along the length of the Yb fiber, it is found that robust operation at 1018 nm can be achieved for a high Yb³⁺-ion excitation density greater than 11.5%, accompanied by high suppression of the feedback from the fiber's end facet. The Yb fiber laser constructed in house yields 626 W of continuous-wave output at 1018 nm for 729 W of incident pump power, corresponding to a slope efficiency of 86.6%. The prospect for power scaling is considered.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.174-174
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• 2007

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.539-542
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• 2011

Thin-film transistors (TFTs) are fabricated using an amorphous indium gallium zinc oxide (a-IGZO) channel layer by rf-magnetron sputtering. Oxygen partial pressure significantly changed the transfer characteristics of a-IGZO TFTs. Measurements performed on a-IGZO TFT show the change of threshold voltage in the transistor channel layer and electrical properties with varying $O_2$ ratios. The device performance is significantly affected by adjusting the $O_2$ ratio. This ratio is closely related with the modulation generation by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.578-578
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• 2012

Graphene, a flat one-atom-thick two-dimensional layer of carbon atoms, is considered to be a promising candidate for nanoelectronics due to its exceptional electronic properties. Most of all, future nanoelectronics such as flexible displays and artificial electronic skins require low cost manufacturing process on flexible substrate to be integrated with high resolutions on large area. The solution based printing process can be applicable on plastic substrate at low temperature and also adequate for fabrication of electronics on large-area. The combination of printed electronics and graphene has allowed for the development of a variety of flexible electronic devices. As the first step of the study, we prepared the gate electrodes by printing onto the gate dielectric layer on PET substrate. We showed the performance of graphene field-effect transistor with electrohydrodynamic (EHD) inkjet-printed Ag gate electrodes.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.61-61
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• 2011

Polymer solar cells have become one of the rising next generation solar cells due to their potential for lightweight and bendable plastic solar modules. Recently, the power conversion efficiency of polymer solar cells has reached ~8 %, which can make ~6 % plastic solar modules when it comes to the modular aperture ratio of ~80 %. Although this efficiency is far behind that of conventional inorganic solar cells, the plastic solar modules are expected to create new energy market into which the inorganic solar modules could not make inroads. In the near future, the plastic solar modules can be integrated with consumer electronics that should overcome the regulation of energy consumption. For this application, the polymer solar cells should be fabricated in a variety of module shapes, which can be resolved by employing conventional and/or advanced coating and molding technologies of plastics products. In this tutorial, the fundamental aspect of polymer solar cells will be briefly introduced and then recent trends in terms of materials and devices will be reviewed together with showing recent results in organic nanoelectronics laboratory.

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.4.2-4.2
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• 2008

• Proceedings of the Korean Magnestics Society Conference
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• 2006.11a
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• pp.124-124
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• 2006

• Proceedings of the Korean Magnestics Society Conference
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• 2007.12a
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• pp.13-13
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.