• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.291-291
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• 2010

Electron-beam lithography (EBL) process is a versatile tool for a fabrication of nanostructures, nano-gap electrodes or molecular arrays and its application to nano-device. However, it is not appropriate for the fabrication of sub-5 nm features and high-aspect-ratio nanostructures due to the limitation of EBL resolution. In this study, the precision assembly and alignment of DNA molecule was demonstrated using sub-5 nm nanostructures formed by a combination of conventional electron-beam lithography (EBL) and plasma ashing processes. The ma-N2401 (EBL-negative tone resist) nanostructures were patterned by EBL process at a dose of $200\;{\mu}C/cm2$ with 25 kV and then were ashed by a chemical dry etcher at microwave (${\mu}W$) power of 50 W. We confirmed that this method was useful for sub-5 nm patterning of high-aspect-ratio nanostructures. In addition, we also utilized the surface-patterning technique to create the molecular pattern comprised 3-(aminopropyl) triethoxysilane (APS) as adhesion layer and octadecyltrichlorosilane (OTS) as passivation layer. DNA-templated gold nanoparticle chain was attached only on the sub-5 nm APS region defined by the amine groups, but not on surface of the OTS region. We were able to obtain DNA molecules aligned selectively on a SiO2/Si substrate using atomic force microscopy (AFM).

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.351-351
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• 2011

Graphene has drawn great interests because of its distinctive band structure and physical properties[1]. A few of the practical applications envisioned for graphene include semiconductor applications, optoelectronics (sola cell, touch screens, liquid crystal displays), and graphene based batteries/super-capacitors [2-3]. Recent work has shown that excellent electronic properties are exhibited by large-scale ultrathin graphite films, grown by chemical vapor deposition on a polycrystalline metal and transferred to a device-compatible surface[4]. In this paper, we focussed our scope for the understanding the graphene growth at different conditions, which enables to control the growth towards the application aimed. The graphene was grown using chemical vapor deposition (CVD) with methane and hydrogen gas in vacuum furnace system. The grown graphene was characterized using a scanning electron microscope(SEM) and Raman spectroscopy. We changed the growth temperature from 900 to $1050^{\circ}C$ with various gas flow rate and composition rate. The growth condition for larger domain will be discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.198-198
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• 2012

Graphene has been the subject of intense study in recent years owing to its good optoelectronic properties, possibility for stretchable electronics, and so on. Especially, many research groups have studied about graphene nanostructures with various sizes and shapes. Graphene needs to be fabricated into useful devices with controllable electrical properties for its successful device applications. However, this been far from satisfaction owing to a lack of reliable pattern transfer techniques. Photolithography, nanowire etching, and electron beam lithography methods are commonly used for construction of graphene patterns, but those techniques have limitations for getting controllable GNRs. We have developed a novel nanoscale pattern transfer technique based on an electro-hydrodynamic lithography providing highly scalable versatile pattern transfer technique viable for industrial applications. This technique was exploited to fabricate nanoscale patterned graphene structures in a predetermined shape on a substrate. FE-SEM, AFM, and Raman microscopy were used to characterize the patterned graphene structures. This technique may present a very reliable high resolution pattern transfer technique suitable for graphene device applications and can be extended to other inorganic materials.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.699-704
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• 2018

One-dimensional nanostructures have attracted increasing attention because of their unique electronic, optical, optoelectrical, and electrochemical properties on account of their large surface-to-volume ratio and quantum confinement effect. Vertically grown nanowires have a large surface-to-volume ratio. The vapor-liquid-solid (VLS) process has attracted considerable attention for its self-alignment capability during the growth of nanostructures. In this study, vertically aligned silicon oxide nano-pillars were grown on Si\$SiO_2$(300 nm)\Pt substrates using two-zone thermal chemical vapor deposition system via the VLS process. The morphology and crystallographic properties of the grown silicon oxide nano-pillars were investigated by field emission scanning electron microscopy and transmission electron microscopy. The diameter and length of the grown silicon oxide nano-pillars were found to be dependent on the catalyst films. The body of the silicon oxide nano-pillars exhibited an amorphous phase, which is consisted with Si and O. The head of the silicon oxide nano-pillars was a crystalline phase, which is consisted with Si, O, Pt, and Ti. The vertical alignment of the silicon oxide nano-pillars was attributed to the preferred crystalline orientation of the catalyst Pt/Ti alloy. The vertically aligned silicon oxide nano-pillars are expected to be applied as a functional nano-material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• Journal of Powder Materials
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• v.17 no.4
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• pp.342-346
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• 2010

In the present work, water-based gold nanofluids were synthesized by the solution plasma processing (SPP). The size distribution and the shape of gold nanoparticles in the nanofluids were investigated using high resolution transmission electron microscopy (HR-TEM). The dispersion stability of gold nanofluids was characterized using zeta potential, as well. The thermal properties of gold nanofluids were measured by utilizing lambda measurement device. Nanofluids containing nanoparticles with $64.0{\pm}42.1\;nm{\sim}18.10{\pm}5.0\;nm$ in diameter were successfully synthesized. As diameter of nanoparticles decreased, dispersion stability of nanofluids increased and the enhanced ratio of thermal conductivity increased. The nanofluid with nanoparticles of $18.10\;{\pm}\;5.0\;nm$ in diameter showed approximately 3% improvement in thermal conductivity measurement and this could be due to the enhanced Brownian movement.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.183-187
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• 2005

Thin films of diblock copolymers may be suitable for semiconductor device applications since they enable patterning of ordered domains with dimensions below photolithographic resolution over wafer-scale area. We obtained nanometer-scale cylindrical structure of dibock copolymer of polystyrene-block-poly(methylmethacrylate), PS-b-PMMA, also demonstrate pattern transfer of the nanoporous polymer using both reactive ion etching. The size of fabricated naonoholes were about 10 nm. Fabricated nanopattern surface was observed by field emission scanning electron microscope (FESEM).

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.164-171
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• 2018

In this study, we have fabricated pure titanium (Ti)/hydroxyapatite (HA) double layer coating on medical grade PEEK from magnetron sputtering system, an investigation was performed whether the surface can be had more improve bio-active for orthopedi/dental applications than that of non-coated one. Pure Ti and HA coating layer were obtained by a radio-frequency and direct current power magnetron sputtering system. The microstructures surface, mechanical properties and wettability of the pure Ti/HA double layer deposited on the PEEK were analyzed by scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDS), X-ray diffraction (XRD), nano-indentation, and contact angle test. According to the EDS and XRD results, the composition and crystal structure of pure Ti and HA coated surface were verified. The elastic modulus and hardness value were increased by pure Ti and HA coating, and the pure Ti/HA double layer coating surface has the highest value. The contact angle showed higher value for pure Ti/HA double layered coating specimens than that of non-coated (PEEK) surface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.32-40
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• 2004

An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the $Si/SiO_2$ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.