• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2013년도 춘계학술대회 논문집
• /
• pp.97-97
• /
• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• 한국분말재료학회지
• /
• 제24권4호
• /
• pp.292-297
• /
• 2017

A metallic oxide layer of a heat-resistant element contributes to the high-temperature oxidation resistance by delaying the oxidation and has a positive effect on the increase in electrical resistivity. In this study, green compacts of Fecralloy powder mixed with amorphous and crystalline silica are oxidized at $950^{\circ}C$ for up to 210 h in order to evaluate the effect of metal oxide on the oxidation and electrical resistivity. The weight change ratio increases as per a parabolic law, and the increase is larger than that observed for Fecralloy owing to the formation of Fe-Si, Fe-Cr composite oxide, and $Al_2O_3$ upon the addition of Si oxide. Si oxides promote the formation of $Al_2O_3$ and Cr oxide at the grain boundary, and obstruct neck formation and the growth of Fecralloy particles to ensure stable electrical resistivity.

• 한국진공학회지
• /
• 제21권5호
• /
• pp.273-278
• /
• 2012

현재 Hf (Hafnium)을 기반으로한 게이트 유전체의 연구는 여러 분야에서 다양하게 진행되어져 왔다. 이는 기존의 $SiO_2$보다 유전상수 값이 크고, 또한 계속되는 scaling-down 공정에서도 양자역학적인 터널링을 차단하는 특성이 뛰어나기 때문이다. MOSFET 구조에서 유전체 박막의 두께 감소로 인한 전기적 특성 저하를 보완하기 위해서 high-K 재료가 대두되었고 현재 주를 이루고 있다. 그러나 현재까지 $HfO_2$에 대한 nano-mechanical 특성 연구는 부족한 상태이므로 본 연구에서는 게이트 절연층으로 최적화하기 위하여 $HfO_2$ 박막의 nano-mechanical properties를 자세히 조사하였다. 시료는 rf magnetron sputter를 이용하여 Si (silicon) 기판 위에 Hafnium target으로 산소유량(4, 8 sccm)을 달리하여 증착하였고, 이후 furnace에서 400에서 $800^{\circ}C$까지 질소분위기에서 20분간 열처리를 실시하였다. 실험결과 산소 유량을 8 sccm으로 증착한 시료가 열처리 온도가 증가할수록 누설전류 특성 성능이 우수 해졌다. Nano-indenter로 측정하고 Weibull distribution으로 정량적 계산을 한 결과, $HfO_2$ 박막의 stress는 as-deposited 시료를 기준으로 $400^{\circ}C$에서는 tensile stress로 변화되었다. 그러나 온도가 증가(600, $800^{\circ}C$)할수록 compressive stress로 변화 되었다. 특히, $400^{\circ}C$ 열처리한 시료에서 hardness 값이 (산소유량 4 sccm : 5.35 GPa, 8 sccm : 5.54 GPa) 가장 감소되었다. 반면에 $800^{\circ}C$ 열처리한 시료에서는(산소유량 4 sccm : 8.09 GPa, 8 sccm : 8.17 GPa) 크게 증가된 것을 확인하였다. 이를 통해 온도에 따른 $HfO_2$ 박막의 stress 변화를 해석하였다.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2016년도 추계학술대회 논문집
• /
• pp.107-107
• /
• 2016

TiCrAlSiN films were developed in order to improve the high-temperature oxidation resistance, corrosion resistance, and mechanical properties of conventional TiN films that are widely used as hard films to protect and increase the lifetime and performance of cutting tools or die molds. In this study, a nano-multilayered TiAlCrSiN film was deposited by cathodic arc plasma deposition. It displayed relatively good oxidation resistance at $700-900^{\circ}C$, owing to the formation protective oxides of $Al_2O_3$, $Cr_2O_3$, and $SiO_2$, and semiprotective $TiO_2$. At $1000^{\circ}C$, the increased temperature led to the formation of the imperfect oxide scale that consisted primarily of the outer ($TiO_2$,$Al_2O_3$)-mixed scale and inner ($TiO_2$, $Al_2O_3$, $Cr_2O_3$)-mixed scale.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.24-25
• /
• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2015년도 춘계학술대회 논문집
• /
• pp.171-172
• /
• 2015

$Ni-W-Si_3N_4$ alloy composite coatings were prepared by pulse electro-deposition method using nickel sulfate bath with different contents of tungsten source, $Na_2WO_4.2H_2O$, and dispersed $Si_3N_4$ nano-particles. The structure and micro-structure of coatings was separately analyzed by X-ray diffraction (XRD) and scanning electron microscope (SEM). Results indicated that nano $Si_3N_4$ and W content in alloy had remarkable effect on micro-structure, micro-hardness and scratch resistant properties. Tungsten content in Ni-W and $Ni-W-Si_3N_4$ alloy ranged from 7 to 14 at.%. Scratch test results suggest that as compared to Ni-W only, $Ni-W-Si_3N_4$ prepared from Ni/W molar ratio of 1:1.5 dispersed with 20 g/L $Si_3N_4$ has shown the best result among different samples.

• 한국재료학회지
• /
• 제22권2호
• /
• pp.61-65
• /
• 2012

A $Li_2O-2SiO_2$ ($LS_2$) glass was investigated as a lithium-ion conducting oxide glass, which is applicable to a fast ionic conductor even at low temperature due to its high mechanical strength and chemical stability. The $Li_2O-2SiO_2$ glass is likely to be broken into small pieces when quenched; thus, it is difficult to fabricate a specifically sized sample. The production of properly sized glass samples is necessary for device applications. In this study, we applied spark plasma sintering (SPS) to fabricate $LS_2$ glass samples which have a particular size as well as high transparency. The sintered samples, $15mm\phi{\times}2mmT$ in size, ($LS_2$-s) were produced by SPS between $480^{\circ}C$ and $500^{\circ}C$ at 45MPa for 3~5mim, after which the thermal and dielectric properties of the $LS_2$-s samples were compared with those of quenched glass ($LS_2$-q) samples. Thermal behavior, crystalline structure, and electrical conductivity of both samples were analyzed by differential scanning calorimetry (DSC), X-ray diffraction (XRD) and an impedance/gain-phase analyzer, respectively. The results showed that the $LS_2$-s had an amorphous structure, like the $LS_2$-q sample, and that both samples took on the lithium disilicate structure after the heat treatment at $800^{\circ}C$. We observed similar dielectric peaks in both of the samples between room temperature and $700^{\circ}C$. The DC activation energies of the $LS_2$-q and $LS_2$-s samples were $0.48{\pm}0.05eV$ and $0.66{\pm}0.04eV$, while the AC activation energies were $0.48{\pm}0.05eV$ and $0.68{\pm}0.04eV$, respectively.

• 한국재료학회지
• /
• 제18권7호
• /
• pp.379-383
• /
• 2008

We report on the light-emitting diode (LED) characteristics of core-shell CdSe/ZnS nanocrystal quantum dots (QDs) embedded in $TiO_2$thin films on a Si substrate. A simple p-n junction could be formed when nanocrystal QDs on a p-type Si substrate were embedded in ${\sim}5\;nm$ thick $TiO_2$ thin film, which is inherently an n-type semiconductor. The $TiO_2$ thin film was deposited over QDs at $200^{\circ}C$ using plasma-enhanced metallorganic chemical vapor deposition. The LED structure of $TiO_2$/QDs/Si showed typical p-n diode currentvoltage and electroluminescence characteristics. The colloidal core-shell CdSe/ZnS QDs were synthesized via pyrolysis in the range of $220-280^{\circ}C$. Pyrolysis conditions were optimized through systematic studies as functions of synthesis temperature, reaction time, and surfactant amount.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
• /
• pp.3-4
• /
• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• 한국전기전자재료학회논문지
• /
• 제18권12호
• /
• pp.1069-1074
• /
• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.