• 대한전자공학회논문지
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• 제24권2호
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• pp.242-247
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• 1987

Electrophysical phenomena at the silicon semiconductor-electrolyte solution interfaces were analyzed based on the zeta potential of the electrical double layer and microelectrophoresis. The suspensions were composed of the p or n-type silicon particles suspended in the KCI or pH buffer solutions. The approximate diameter of the prepared and sampled sioicon semiconductor pardticles was 1.5\ulcorner. The sign of the zeta poetntials of the p and n-type silicon particles in the KCl and pH buffer solution was positive. A range of electrophoretic mobilities of the p and n-type silicons in the KCl solutions was 5.5-8.9x10**-4 cm\ulcornerV-sec and 4.2-7.9x10**-4cm\ulcornerV-sec, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 70.4-114.0mV nad 53.9-101.2mV, respectively. On the other hand, a range of electrophoretic mobilities of the p and n-type silicons in the pH buffer solutions was 1.1x10**-4-2.2x10**-3cm\ulcornerV-sec and 0-2.1x10**-3cm\ulcornerV-sec, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 14.1-281.6mV and 0-268.8mV, respectively. The zeta potentials and electrical double layers of the doped silicon semiconductors are decisively influenced by the positively charged ions in the solutions. The maximum values of the zeta potentials in the KCl solutions appeared at a concentration of about 10-\ulcorner. The isoelectric point of the n-type silicon semiconductors appeared at about a pH 7. The effect of the space charge of the doped silicon semiconductors can be neglected compare with the effect of the surface charge.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.295-301
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• 2002

In this paper, solenoid-type 3-D passives (inductors and transformers) have been designed, fabricated, and characterized by using electroplating techniques, wire bonding techniques, multi-layer thick photoresist, and low temperature processes which are compatible with semiconductor circuitry fabrication. Two different fabrication approaches are performed to develop the solenoid-type 3-D passives and relationship of performance characteristics and geometry is also deeply investigated such as windings, cross-sectional area of core, spacing between windings, and turn ratio. Fully integrated inductor has a quality factor of 31 at 6 GHz, an inductance of 2.7 nH, and a self resonant frequency of 15.8 GHz. Bonded wire inductor has a quality factor of 120, an inductance of 20 nH, and a self resonant frequency of 8 GHz. Integrated transformers with turn ratios of 1:1 and n:l have the minimum insertion loss of about 0.6 dB and the wide bandwidth of a few GHz.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Current Applied Physics
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• 제18권12호
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• pp.1546-1552
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• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
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• pp.109-112
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• 2007

In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• 대한화학회지
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• 제54권4호
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• pp.380-386
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• 2010

황산 용액에서 양극산화(anodization)에 의하여 생성되는 산화피막의 생성과정(growth kinetics)과 이 피막의 전기적 성질을 전기화학적 임피던스 측정법(electrochemical impedance spectroscopy)으로 조사하였다. 산화피막은 $Al_2O_3$로 점-결함 모형(point defect model)에 따라 성장하였으며, n-형 반도체의 전기적 성질을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
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• pp.17-21
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• 2001

We proposed that concentrations of cartier electron as well as ionized donor defects in nonstoichiometric ZnO are proportional to $P^{-1/2}_{O_2}$, whenever they ionizes singly or doubly, by employing the Fermi-Dirac (FD) statistics for ionization of the native thermal defects $Zn_i$ and $V_o$. The effect of acceptor defect, zinc vacancy $V_{Zn}$made by the Frenkel and Schottky disorder reactions, on carrier concentrations was discussed. By application of the FD statistics law to their ionization while the formation of defects is assumed governed by the mass-action law, the calculation results indicate; 1. ZnO shows n-type conductivity with $N_D>$N_A$ and majority concentration of $n{\propto}\;P^{-1/2}_{O_2}$ in a range of $P_{O_2}$, lower than a critical value. 2. As the concentration of acceptor $V_{Zn}$ increases proportional to $P^{1/2}_{O_{2}}$, ZnO made at extremely high $P_{O_{2}}$, can have p-type conductivity with majority concentration of p ${\propto}\;P^{-1/2}_{O_{2}}$. One may not, however, obtain p-type ZnO if the pressure for $N_{D}<$N_{A}$ is too high.

• 센서학회지
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• 제30권5호
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2006년도 High Temperature Superconductivity Vol.XVI
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• pp.18-18
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• 2006