• Journal of Information Display
• /
• v.8 no.4
• /
• pp.15-18
• /
• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.16-19
• /
• 2007

In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analyzed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.2
• /
• pp.12-16
• /
• 2000

The electrical characteristics of n-channel LDD structured poly-Si TFT's have been systematically investigated. It have been found that the LDD regions act as the effect of series resistance and reducing the electric field. Kink effect is disappeared and off current is greatly reduced, while on current is slightly reduced. On/off current ratio graph shows that LDD device's switching characteristic is better than that of conventional device. As a result of study, it is concluded that the effect of electric field's reduction is more dominant than that of series resistance.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1999.11a
• /
• pp.148-148
• /
• 1999

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.933-936
• /
• 2000

N-channel poly-Si TFT, processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5um and 3um poly-Si TFT’s are 3.3V, 37V respectively. With the threshold voltage shift, the degradation of transconductance and subthreshold swing is also observed.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.287-287
• /
• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• Journal of Sensor Science and Technology
• /
• v.12 no.5
• /
• pp.218-224
• /
• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.05a
• /
• pp.403-406
• /
• 1999

The influence of temperature variation (25～125$^{\circ}C$) on poly-Si thin-film transistors (TFT's) was investigated by examining the electrical properties change of poly-Si films formed by solid phase crystallization (SPC). The n-channel poly-Si TFT's fabricated by SPC with channel length of 1.5 and loon ,respectively, exhibit good characteristics with a high ${\mu}$$\sub$FE/ ($\geq$82 and $\geq$60$\textrm{cm}^2$/V-s in 1.5 and 10$\mu\textrm{m}$, respectively), low V$\sub$t/, ($\leq$1.52 and $\leq$ 2.75V in 1.5 and 10$\mu\textrm{m}$, respectively), low S$\sub$t/, and good ON-OFF characteristics in spite of temperature variation. Thus, poly-Si films formed by SPC can be applied for the application to poly-Si TFT liquid crystal display with peripheral integrated circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05a
• /
• pp.53-56
• /
• 2004

The a-Si:H TFT using ferroelectric of SrTi $O_3$as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$and S $i_3$ $N_4$. Ferroelctric increases on-current, decreases thresh old voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, refractive index of 1.8~2.0 and resistivity of 10$^{13}$ - 10$^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60~100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8~20${\mu}{\textrm}{m}$ and channel width of 80~200${\mu}{\textrm}{m}$. And it shows that drain current is 3.4$mutextrm{A}$ at 20 gate voltage, $I_{on}$ / $I_{off}$ is a ratio of 10$^{5}$ - 10$^{8}$ and $V_{th}$ is 4~5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $mutextrm{A}$ at 20 gate voltage and $V_{th}$ is 5~6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.zed.d.

• Journal of Sensor Science and Technology
• /
• v.2 no.1
• /
• pp.95-99
• /
• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.