• 제목/요약/키워드: multipliers

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Low Area and High Performance Multi-mode 1D Transform Block Design for HEVC (HEVC를 위한 저면적 고성능 다중 모드 1D 변환 블록 설계)

  • Kim, Ki-Hyun;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.78-83
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    • 2014
  • This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

An Estimation of Economic Base Multipliers of Rural Centers (농촌중심지의 경제기반승수 추정)

  • Kim, Hak-Hoon
    • Journal of the Korean Regional Science Association
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    • v.35 no.4
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    • pp.3-18
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    • 2019
  • This study estimates the levels of the basic and nonbasic activities in five rural centers in Cheongwon County by using the direct survey method and indirect non-survey methods. The economic base multipliers obtained through direct survey method and indirect non-survey methods are compared to find out the advantages and disadvantages of the estimation methods. There are some limitations in applying non-survey methods for economic base estimation. It is found that, among three non-survey methods, multipliers obtained through minimum requirements method are better than other two methods in terms of the theoretical assumption. However, if we use direct survey data and in-commuter/out-commuter data, we can obtain more accurate multiplier estimates.

The Economic Impact Analysis of Rural Tourism Development Projects (농촌관광마을 육성사업의 경제적 파급효과 분석)

  • Son, Eun-Ho;Park, Duk-Byeong;Yoon, Jun-Sang
    • Journal of Agricultural Extension & Community Development
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    • v.21 no.3
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    • pp.155-179
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    • 2014
  • Input-output(I-O) analysis is now widely used to examine the economic impact of tourism. The study aims to demonstrate the impact of agri-tourism development project on local development in terms of income and employment. Based on the I-O transactions tables developed by Bank of Korea (2011), rural tourism related sectoral multipliers were derived with respect to output, income, employment, and value-added tax. The results of the I-O model indicate that in 2011, rural tourism development generated 1,387 billion Won of output impact, 287 billion Won of income impact, 275 billion Won of value-added impact, and 41,127 full-time jobs, respectively throughout direct, indirect, and induced effects. In particular, the restaurant sector had relative higher output and employment multipliers as compared to other industries, whereas they had lower multipliers of income and value-added than any other industries. The findings imply that the restaurant sector was relatively labor-intensive industry, generating high impact of employment effects.

Sign-Extension Reduction Method in Common Subexpression Elimination Circuit (Common Subexpression Elimination 회로의 부호 확장 제거)

  • Kim, Yong-Eun;Chung, Jin-Gyun;Lee, Moon-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.65-70
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    • 2008
  • In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

A Cost-Effective and Accurate COA Defuzzifier Without Multipliers and Dividers (승산기 및 제산기 없는 저비용 고정밀 COA 비퍼지화기)

  • 김대진;이한별;강대성
    • Journal of the Korean Institute of Intelligent Systems
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    • v.8 no.2
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    • pp.70-81
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    • 1998
  • This paper proposes an accurate and cost-effective COA defuzzifier of fuzzy logic controller (FLC). The accuracy of the proposed COA defuzzifier is obtained by involving both membership values and spans of membership functions in calculating a crisp value. The cost-effectiveness of the proposed COA defuzzifier is obtained by replacing the division in the COA defuzzifier by finding an equilibrium point of both the left and right moments. The proposed COA defuzzifier has two disadvantages that it ncreases the hardware complexity due to the additional multipliers and it takes a lot of computation time to find the moment equilibrium point. The first disadvantage is overcome by replacing the multipliers with the stochastic AND operations. The second disadvantage is alleviated by using a coarse-to-fine searching algorithm that accelerates the finding of moment equilibrium point. Application of the proposed COA defuzzifier to the truck backer-upper control problem is performed in the VHDL simulation and the control accuracy of the proposed COA defuzzifier is compared with that of the conventional COA defuzzifier in terms of average tracing distance.

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High-performance Pipeline Architecture for Modified Booth Multipliers (Modified Booth 곱셈기를 위한 고성능 파이프라인 구조)

  • Kim, Soo-Jin;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.36-42
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    • 2009
  • This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.

Fast Fourier Transform Processor based on Low-power and Area-efficient Algorithm (저 전력 및 면적 효율적인 알고리즘 기반 고속 퓨리어 변환 프로세서)

  • Oh Jung-yeol;Lim Myoung-seob
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.2 s.302
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    • pp.143-150
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    • 2005
  • This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

A Study on the Evaluation of Horizontal, Vertical, Asymmetric and Coupling Multipliers of the NIOSH Lifting Equation in Korean Male (한국인 20대 남성의 NIOSH Lifting Equation 계수평가에 관한 연구)

  • Bae, Dong-Chul;Kim, Yong-Jae
    • Journal of the Korean Society of Safety
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    • v.24 no.2
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    • pp.83-88
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    • 2009
  • The objective of this paper was to evaluate the effectiveness of horizontal, vertical, asymmetric and coupling multipliers for manual material handling. Lifting tasks with 5 different horizontal distances ($30{\sim}70cm$) for 6 vertical distances(ankle, knee, waist, elbow, shoulder and head height) were experimented. The muscle activity and muscle exertion level during asymmetric load handling(without trunk flexion) was experimented. Lifting tasks with and without handle tote box for three postures(straight, bending, right angle posture) were experimented. The degrading tendency did not appeared almost in $60{\sim}70cm$ interval's horizontal distance. As a result of ANOVA, MVC paid attention to horizontal and vertical distance but cross effect was insignificant(p<0.01). The change of the MVC according to the horizontal, vertical distance appeared similar from of RWL. The results of normalized MVC measurement were decreased about 16%, 24%, 34% respectively as the asymmetry angle was $30^{\circ}$, $60^{\circ}$, $90^{\circ}$. RMS EMG values of right erector spinae muscles were decreased as the work posture went to $90^{\circ}$ and those of left erector spinae muscles were increased until the asymmetry angle was $40^{\circ}$ but decreased continually over $40^{\circ}$. 7 subjects, activities of left and right latissimus dorsi muscles were maintained constantly, while for remainer, those were irregular. MVC reduced maximum 23% by type of handle. MVC was highest in straight posture, but was lowest in right angle posture. As a result of ANOVA, MVC paid attention to posture, coupling(p<0.01). To all handle types, biceps brachii activity was increased in right angle posture, but reduced in straight posture. Based on the results of this study, it is suggested that the NIOSH guideline should not be directly applied to Korean without reasonable reexamination. In addition, we need to afterward study through an age classification.

On the use of the Lagrange Multiplier Technique for the unilateral local buckling of point-restrained plates, with application to side-plated concrete beams in structural retrofit

  • Hedayati, P.;Azhari, M.;Shahidi, A.R.;Bradford, M.A.
    • Structural Engineering and Mechanics
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    • v.26 no.6
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    • pp.673-685
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    • 2007
  • Reinforced concrete beams can be strengthened in a structural retrofit process by attaching steel plates to their sides by bolting. Whilst bolting produces a confident degree of shear connection under conditions of either static or seismic overload, the plates are susceptible to local buckling. The aim of this paper is to investigate the local buckling of unilaterally-restrained plates with point supports in a generic fashion, but with particular emphasis on the provision of the restraints by bolts, and on the geometric configuration of these bolts on the buckling loads. A numerical procedure, which is based on the Rayleigh-Ritz method in conjunction with the technique of Lagrange multipliers, is developed to study the unilateral local buckling of rectangular plates bolted to the concrete with various arrangements of the pattern of bolting. A sufficient number of separable polynomials are used to define the flexural buckling displacements, while the restraint condition is modelled as a tensionless foundation using a penalty function approach to this form of mathematical contact problem. The additional constraint provided by the bolts is also modelled using Lagrange multipliers, providing an efficacious method of numerical analysis. Local buckling coefficients are determined for a range of bolting configurations, and these are compared with those developed elsewhere with simplifying assumptions. The interaction of the actions in bolted plates during buckling is also considered.

Efficient Bit-Parallel Polynomial Basis Multiplier for Repeated Polynomials (반복 기약다항식 기반의 효율적인 비트-병렬 다항식 기저 곱셈기)

  • Chang, Nam-Su;Kim, Chang-Han;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.19 no.6
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    • pp.3-15
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    • 2009
  • Recently, Wu proposed a three small classes of finite fields $F_{2^n}$ for low-complexity bit-parallel multipliers. The proposed multipliers have low-complexities compared with those based on the irreducible pentanomials. In this paper, we propose a new Repeated Polynomial(RP) for low-complexity bit-parallel multipliers over $F_{2^n}$. Also, three classes of Irreducible Repeated polynomials are considered which are denoted, respectively, by case 1, case 2 and case3. The proposed RP bit-parallel multiplier has lower complexities than ones based on pentanomials. If we consider finite fields that have neither a ESP nor a trinomial as an irreducible polynomial when $n\leq1,000$. Then, in Wu''s result, only 11 finite fields exist for three types of irreducible polynomials when $n\leq1,000$. However, in our result, there are 181, 232, and 443 finite fields of case 1, 2 and 3, respectively.