Browse > Article

Sign-Extension Reduction Method in Common Subexpression Elimination Circuit  

Kim, Yong-Eun (Div. of Electronic & Information Engineering Chonbuk National University)
Chung, Jin-Gyun (Div. of Electronic & Information Engineering Chonbuk National University)
Lee, Moon-Ho (Div. of Electronic & Information Engineering Chonbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.9, 2008 , pp. 65-70 More about this Journal
Abstract
In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.
Keywords
Multiplierless Filter; Common subexpression elimination; Sign extension;
Citations & Related Records
연도 인용수 순위
  • Reference
1 R. Hartley, "Subexpression sharing in filters using canonic signed digit multipliers," IEEE Trans. on Circuits and Syst. II, vol. 43, Oct. 1996
2 A. Dempster and M. D. Macleod, "Use of minimum adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol. 42, pp569-557, Sept. 1995   DOI   ScienceOn
3 I. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, NJ: Prentice-Hall International, Inc. 1993
4 A. Dempster and M. D. Macleod, "Constant integer multiplication using minimum adders, " Proc. Inst. Elec. Eng. Circuits and Systems, vol. 141, no. 5, pp.407-413, Oct. 1994
5 Marcos Martinez-Peiro, Eduardo I. Boemo, and Lars Wanhammar, "Design of high-speed multiplierless filter using a nonrecursive signed common subexpression algorithm, " IEEE Transactions on Circuits and Systems II, vol. 49, pp. 196-203. 2002   DOI   ScienceOn
6 Sang-Min Kim, Jin-Gyun Chung, and Keshab K. Parhi, "Low error fixed-width CSD multiplier with efficient sign extension", IEEE Transactions on Circuit and System-II, vol.50, no.12, pp.984-993 dec. 2003
7 M. Mehendale, S. D. Sherlekar, and G. Vekantesh, "Systhesis of multiplierless FIR filters with minimum number of additions, " in Proc. 1995, IEEE/ACM Int. Conf. Computer-Aided Design, Los Alamitos, CA, pp. 668-671. 1995
8 C. S. Wallace, "Suggestion for a fast multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, pp. 14-17, 1964   DOI   ScienceOn
9 M. Potkonjak et al., "Multiple constant multiplication: efficient and versatile freamework and algorithms for exploring common subexpression elimination," IEEE Trans. Computer-Aided Design, vol. 15, no. 2, pp. 151-165, Feb. 1996   DOI   ScienceOn
10 Marcos Martínez-Peiró, Eduardo I. Boemo, and Lars Wanhammar, "Design of High-Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm" IEEE Transactions on Circuits and Systems II, vol. 49, pp. 198. 2002