• Title/Summary/Keyword: multipliers

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Nonlinear dynamic FE analysis of structures consisting of rigid and deformable parts -Part I - Formulation

  • Rojek, J.;Kleiber, M.
    • Structural Engineering and Mechanics
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    • v.2 no.4
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    • pp.313-326
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    • 1994
  • Some structures under the action of some specific loads can be treated as consisting of rigid and deformable parts. The paper presents a way to include rigid elements into a finite element model accounting for geometrical and material nonlinearities. Lagrange multipliers technique is used to derive equations of motion for the coupled deformable-rigid system. Solution algorithm based on the elimination of the Lagrangian multipliers and dependent kinematic unknowns at the element level is described. A follow-up paper(Rojek and Kleiber 1993) complements the discussion by giving details of the computer implementation and presenting some realistic test examples.

Subquadratic Space Complexity Multiplier for GF($2^n$) Using Type 4 Gaussian Normal Bases

  • Park, Sun-Mi;Hong, Dowon;Seo, Changho
    • ETRI Journal
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    • v.35 no.3
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    • pp.523-529
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    • 2013
  • Subquadratic space complexity multipliers for optimal normal bases (ONBs) have been proposed for practical applications. However, for the Gaussian normal basis (GNB) of type t > 2 as well as the normal basis (NB), there is no known subquadratic space complexity multiplier. In this paper, we propose the first subquadratic space complexity multipliers for the type 4 GNB. The idea is based on the fact that the finite field GF($2^n$) with the type 4 GNB can be embedded into fields with an ONB.

Efficient VLSI architecture for one-dimensional discrete wavelet transform using a sealable data reorder unit

  • Park, Taegeun
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.353-356
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    • 2002
  • In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

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A Method of Load Impedance Optimization for High Efficiency Millimeter-wave Range 2nd Harmonic Generation (밀리미터파 대역 제2고조파 고효율 생성을 위한 부하 임피던스의 최적화 방법)

  • Choi, Young-Kyu
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.8
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    • pp.1566-1571
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    • 2011
  • The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

Buckling of insulated irregular transition flue gas ducts under axial loading

  • Ramadan, H.M.
    • Structural Engineering and Mechanics
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    • v.43 no.4
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    • pp.449-458
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    • 2012
  • Finite element buckling analysis of insulated transition flue ducts is carried out to determine the critical buckling load multipliers when subjected to axial compression for design process. Through this investigation, the results of numerical computations to examine the buckling strength for different possible duct shapes (cylinder, and circular-to-square) are presented. The load multipliers are determined through detailed buckling analysis taking into account the effects of geometrical construction and duct plate thickness which have great influence on the buckling load. Enhancement in the buckling capacity of such ducts by the addition of horizontal and vertical stiffeners is also investigated. Several models with varying dimensions and plate thicknesses are examined to obtain the linear buckling capacities against duct dimensions. The percentage improvement in the buckling capacity due to the addition of vertical stiffeners and horizontal Stiffeners is shown to be as high as three times for some cases. The study suggests that the best location of the horizontal stiffener is at 0.25 of duct depth from the bottom to achieve the maximum buckling capacity. A design equation estimating the buckling strength of geometrically perfect cylindrical-to-square shell is developed by using regression analysis accurately with approximately 4% errors.

Development of Hardware Modules for Montgomery Modular Multipliers based on 32-bit multipliers (32 비트 곱셈기에 기반한 몽고메리 모듈러 곱셈기 하드웨어 모듈 개발)

  • 양인제;김동규
    • Proceedings of the Korea Multimedia Society Conference
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    • 2003.11a
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    • pp.162-165
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    • 2003
  • RSA 등의 공개키 암호화 시스템에서는 매우 큰 정수에 대해서 모듈러 멱승을 수행한다. 그러므로 모듈러 멱승을 효율적으로 구현하기 위하여 많은 연구가 진행되어 왔다. 모듈러 멱승을 소프트웨어적으로 구현할 경우 시간적인 제약을 극복하지 못하므로, 이를 하드웨어로 구현하려는 연구도 많이 이루어지고 있는 추세이다. 몽고메리 곱셈 알고리즘은 비용이 많이 드는 모듈러 연산을 효율적으로 처리하고 있으므로 하드웨어적 구현에 현재 널리 쓰이고 있다. 몽고메리 곱셈 알고리즘은 내부적으로 당연히 곱셈연산을 주로 사용하기 때문에, 어떤 곱셈기를 사용하느냐가 성능에 영향을 미치게 한다. 본 논문에서는 몽고메리 곱셈기를 다양한 32비트 곱셈기를 적용해 보고, 성능 및 면적을 측정하였다. 이러한 측정 결과를 토대로 특정 응용에 알맞은 32비트 곱셈기를 적절히 선택하여 설계할 수 있을 것으로 기대한다.

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A Study on Approximate and Exact Algorithms to Minimize Makespan on Parallel Processors (竝列處理機械상에서 總作業完了時間의 最小化解法에 관한 硏究)

  • Ahn, Sang-Hyung;Lee, Song-Kun
    • Journal of the Korean Operations Research and Management Science Society
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    • v.16 no.2
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    • pp.14-35
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    • 1991
  • The purpose of this study is to develop an efficient exact algorithm for the problem of scheduling n in dependent jobs on m unequal parallel processors to minimize makespan. Efficient solutions are already known for the preemptive case. But for the non-preemptive case, this problem belongs to a set of strong NP-complete problems. Hence, it is unlikely that the polynomial time algorithm can be found. This is the reason why most investigations have bben directed toward the fast approximate algorithms and the worst-case analysis of algorithms. Recently, great advances have been made in mathematical theories regarding Lagrangean relaxation and the subgradient optimization procedure which updates the Lagrangean multipliers. By combining and the subgradient optimization procedure which updates the Lagrangean multipliers. By combining these mathematical tools with branch-and-bound procedures, these have been some successes in constructing pseudo-polynomial time algorithms for solving previously unsolved NP-complete problems. This study applied similar methodologies to the unequal parallel processor problem to find the efficient exact algorithm.

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A Study on Approximate and Exact Algorithms to Minimize Makespan on Parallel Processors (병렬처리리례 상에서 동작업완료시간의 최소화해법에 관한 연구)

  • Ahn, Sang-Hyung;Lee, Song-Kun
    • Journal of the Korean Operations Research and Management Science Society
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    • v.16 no.2
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    • pp.13-35
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    • 1991
  • The purpose of this study is to develop an efficient exact algorithm for the problem of scheduling n in dependent jobs on m unequal parallel processors to minimize makespan. Efficient solutions are already known for the preemptive case. But for the non-preemptive case, this problem belongs to a set of strong NP-complete problems. Hence, it is unlikely that the polynomial time algorithm can be found. This is the reason why most investigations have bben directed toward the fast approximate algorithms and the worst-case analysis of algorithms. Recently, great advances have been made in mathematical theories regarding Lagrangean relaxation and the subgradient optimization procedure which updates the Lagrangean multipliers. By combining and the subgradient optimization procedure which updates the Lagrangean multipliers. By combining these mathematical tools with branch-and-bound procedures, these have been some successes in constructing pseudo-polynomial time algorithms for solving previously unsolved NP-complete problems. This study applied similar methodologies to the unequal parallel processor problem to find the efficient exact algorithm.

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