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http://dx.doi.org/10.5370/KIEE.2011.60.8.1566

A Method of Load Impedance Optimization for High Efficiency Millimeter-wave Range 2nd Harmonic Generation  

Choi, Young-Kyu (신라대 공대 전자공학과)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.60, no.8, 2011 , pp. 1566-1571 More about this Journal
Abstract
The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.
Keywords
Millimeter-wave oscillator; Frequency multiplier; Load impedance; GaAs FET;
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