• Kyungpook Mathematical Journal
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• v.54 no.2
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• pp.321-332
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• 2014

In this article we introduce different types of multiplier I-convergent double sequence spaces. We study their different algebraic and topological properties like solidity, symmetricity, completeness etc. The decomposition theorem is established and some inclusion results are proved.

• Communications of the Korean Mathematical Society
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• v.10 no.3
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• pp.633-642
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• 1995

Recently S. Axler proved that every sequence in the unit disk U converging to the boundary contains an interpolating subsequence for the multipliers of the Dirichlet space D(U). In this paper we generalizes Axler's result to the finitely connected planer domains such that the Dirichlet spaces are contained in the Bergman spaces.

• Korean Journal of Mathematics
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• v.7 no.1
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• pp.45-51
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• 1999

Let X and Y be topological vector spaces. For a sequence {$T_j$} of bounded operators from X into Y the $c_0$-multiplier convergence of ${\sum}T_j$ is an invariant on topologies which are stronger (need not strictly) than the topology of pointwise convergence on X but are weaker (need not strictly) than the topology of uniform convergence on bounded subsets of X.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.906-911
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• 2001

In this paper, LPI(low probability of intercept) and AJ(anti jamming) performance of the chirped BPSK system are analyzed. In the chirp method the cyclostationary of the signal is eliminated, since the instantaneous frequency is varied randomly within the whole spread bandwidth. Therefore, chirp method is considered for good LPI system against DAM(delay-and-multiplier) or SC (squaring circuit) interceptor which detects the chip rate or carrier frequency. Longer chirp duration makes the LPI performance better. From the simulation results, the chirp method has better AJ performance than DS(direct sequence) system in the PBNJ(partial band noise jammer) channel. At the same JSR(jammer to signal power ratio) level, chirped BPSK system has more robust AJ performance against MTJ(multi-tone jammer) than PBNJ.

• Communications of the Korean Mathematical Society
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• v.20 no.1
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• pp.145-159
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• 2005

In this paper we consider the problem of testing statistical hypotheses for unknown parameters in nonlinear regression models and propose three asymptotically equivalent tests based on regression quantiles estimators, which are Wald test, Lagrange Multiplier test and Likelihood Ratio test. We also derive the asymptotic distributions of the three test statistics both under the null hypotheses and under a sequence of local alternatives and verify that the asymptotic relative efficiency of the proposed test statistics with classical test based on least squares depends on the error distributions of the regression models. We give some examples to illustrate that the test based on the regression quantiles estimators performs better than the test based on the least squares estimators of the least absolute deviation estimators when the disturbance has asymmetric and heavy-tailed distribution.

• Journal of the Korean Data and Information Science Society
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• v.8 no.1
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• pp.9-20
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• 1997

Several methods are proposed for optimizing Fourier series estimators with respect to Mean Integrated Square Error metrics. Traditionally, such method have followed. one of two basic strategies; A stopping rules or the rules of determine multipliers. A central hypothesis of this study is that better estimates can be obtained by combining the two strategies. A new multiplier sequence is proposed, which used in conjunction with any of the stopping rules, is shown to improve the performance of estimator which relies solely on a stopping rule.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.291-292
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• 2006

This paper presents rate-distortion optimization that is considered sequence statistics(complexity) to choose the best macroblock mode decision in H.264. In previous work, Lagrange multiplier is derived by the function of constant value 0.85 and QP so that is not the proper Lagrange multilplier for any image sequence. The proposed algorithm solves the problem by changing constant value 0.85 into adaptive value which is influenced by image complexity, and by reducing the encoder complexity to estimate the image statistics with the multiplication of transformed, quantized rate and distortion. Proposed algorithm is achieved the bit-rate saving up to 5% better than previous method.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.899-902
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• 1999

In this paper, we designed a equalizer that moved the multipath of channel in 8-VSB transmission receiver. After doing the initial equalization with "LMS(Least Mean Square)"aigorithm. this equalizer used "Stop-and-Go" algorithm. Because of estimating SER(Symbol to Error Ratio) every a training sequence, this can positively cope with transformation of channel and because of using fast clock than symbol-clock(10.76 MHz), we are able to reduce a multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.