• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.580-598
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• 1987

This paper presents a method to realize the sequential multiple-valued Logic on Galois field. First, We develop so that Taylor series can be corresponded the irreducible polynomial to realize over the finite field, and produce the matrix. This paper object expanded a basic concept of the conbinational Logic circuit so as to apply in the sequential Logic circuit. First of all, We suggest a theory for constructing sequential multiple-valued Logic circuit. Then, We realized the construction with the single input and the multi-output that expanded its function construction. In case of the multi-output, the circuit process by the partition function concept as the mutual independent. This method can be reduced a enormous computer course to need a traditional extention that designed the sequential multi-valued Logic circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.503-510
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• 1989

This paper represents a method which construct Combinational Mutiple Valued Logic circuits. First, it constructs Combinational Multiple Valued Logic Cell as the input variable, Then, it can be applied to the general case by expanding ti, thus these series of process is simple and regular. The construction theory of Combinational Multiple Valued Logic circuits, representes here has regularity, simplicity and modularity, especially, in case imput variables are incresed this theory also has characteristics of expansion.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.589-594
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• 1992

This paper offers the simplification method of Multiple-Valued logic function based on M-AND,M-OR, NOT operation presented by Lukasiewicz. First in performing the simplification the result is different by the method to arrange Cube, the method to find the most effective adjacent term if, most of all, important in simplification. According to this method, the two-variable multiple-valued logic function given by truth table is decomposed. The simplification method in this paper proves that the number of devices and cost is considerably reduced comparing with the existing method 141 to realize the same logic functions.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.32-40
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• 1999

The analysis of logic function is performed by the spectral coefficients which transform the function domain data into the spectral domain data. By using the spectral techniques, analysis of MVL circuits is performaed, and the fault analysis and detecting methods of multiple-valued logic circuits are proposed in this paper.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1274-1276
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• 1993

We have designed a multiple-valued fuzzy Approximate Analogical-Reseaning system (AARS). The system uses a similarity measure of fuzzy sets and a threshold of similarity ST to determine whether a rule should be fired, with a Modification Function inferred from the Similarity Measure to deduce a consequent. Multiple-valued basic fuzzy blocks are used to construct the system. A description of the system is presented to illustrate the operation of the schema. The results of simulations show that the system can perform about 3.5 x 106 inferences per second. Finally, we compare the system with Yamakawa's chip which is based on the Compositional Rule of Inference (CRI) with Mamdani's implication.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.